From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C535836B17; Tue, 13 Feb 2024 11:38:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707824336; cv=none; b=frjGok3Zf0Jqmjquxq/sbLbDlOQESgkpj2oF43oARdl36mwU+Qe4VmhlFcEuGPaSxdUOK2I8juOSYG/qLHoRxNJKmvH43WKT8C7rLqg26XpbLABRrzdtSRJ38Pxov2eOC5eUX35gLxU5G37Lm3Qq0EP3Y/Ebi+5KeNaGgU4uR1Q= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707824336; c=relaxed/simple; bh=5T1R2LaZ7/5RcBfjH8QnKHLDGAacAb4MmSubbGT5Mv0=; h=From:Date:To:cc:Subject:In-Reply-To:Message-ID:References: MIME-Version:Content-Type; b=tTMoh7NlFPgwl32MBuEWT6x+fe1bQ7IzSUyWnaOZOG6G7HaC8ZzvrsKWBE+vRxdIvYNx7A06DWXZS3esYsE+RgM5kYbpkLK/ZGX5e1PQIP8av504+FIJj/+0vUqP7IQKa8NKIdFTU/jrH9+esol7PZkD/7aD4eN0KIr60lZVeaw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=UmlKSDDD; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="UmlKSDDD" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1707824334; x=1739360334; h=from:date:to:cc:subject:in-reply-to:message-id: references:mime-version; bh=5T1R2LaZ7/5RcBfjH8QnKHLDGAacAb4MmSubbGT5Mv0=; b=UmlKSDDDbKInSd3V6t9USBBnMkmAsOIYm4q0jHZgLiowaa9NrRVxodI9 lPTd0SAvwdTwJuNkgmJzvF6JjhcYJ9BTBO0jnOM4GsVXuwZ/p/VxJ1IE0 QxoZDEv5uejLVB/nU+0Ol8QbAVkbihoNhlu9W+X9bWhohf1eUeK4SyEGO xlLFc2voCGVk3XH18iB/WuqHSd7vPX2VNkAzEe/IjBLXa3NcF3Zp6aGGp LgEJyNmm47b06MmuOPpGMsE8GI+2gOgl2kTvYOTqDq7wHkU+sLyNFS42f 2WueYbXfZCT00GvXpZ2DBkRqGD6zXyrqitVEVAuTxdYD16ad4zfTCubHR Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10982"; a="5658718" X-IronPort-AV: E=Sophos;i="6.06,157,1705392000"; d="scan'208";a="5658718" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Feb 2024 03:38:54 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,157,1705392000"; d="scan'208";a="3218807" Received: from ijarvine-desk1.ger.corp.intel.com (HELO localhost) ([10.246.32.103]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Feb 2024 03:38:52 -0800 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Date: Tue, 13 Feb 2024 13:38:47 +0200 (EET) To: Shravan Kumar Ramani cc: Hans de Goede , Vadim Pasternak , David Thompson , platform-driver-x86@vger.kernel.org, LKML Subject: Re: [PATCH v3 3/4] platform/mellanox: mlxbf-pmc: Add support for 64-bit counters and cycle count In-Reply-To: Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Hi, I've applied to first two type cleanup patches to review-ilpo. I considered taking patch 3 and 4 already too but I'd like to see the sysfs documentation for the added sysfs files first. On Tue, 13 Feb 2024, Shravan Kumar Ramani wrote: > Add support for programming any counter to monitor the cycle count. > Since counting of cycles using 32-bit ocunters would result in frequent ocunters -> counters > wraparounds, add the ability to combine 2 adjacent 32-bit counters to > form 1 64-bit counter. > Both these features are supported by BlueField-3 PMC hardware, hence Please try to avoid paragraphs like this. Either make it a truly flowing paragraph or insert a newline in between the paragraphs. > the required bit-fields are exposed by the driver via sysfs to allow > the user to configure as needed. > > Signed-off-by: Shravan Kumar Ramani > Reviewed-by: David Thompson > Reviewed-by: Vadim Pasternak -- i.