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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-493b2766da1sm31255735e9.15.2026.06.29.01.30.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 29 Jun 2026 01:30:57 -0700 (PDT) Message-ID: Date: Mon, 29 Jun 2026 10:30:54 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 00/32] x86/msr: Drop 32-bit MSR interfaces To: =?UTF-8?B?SsO8cmdlbiBHcm/Dnw==?= Cc: "Rafael J . Wysocki" , Daniel Lezcano , Zhang Rui , "lukasz.luba@arm.com" , Jason Baron , Borislav Petkov , Tony Luck , Yazen Ghannam , Len Brown , Pavel Machek , Thomas Gleixner , Ingo Molnar , Dave Hansen , "H. Peter Anvin" , Sean Christopherson , Paolo Bonzini , "Kirill A. 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Those will continue using the same instructions as before >>>> and just change the calling conventions, right? >>> >>> Yes. I thought this would be clear from the following: >>> >>> - They are based on primitives using 64-bit sized values anyway. >> >> Right, that was my reading of it as well, but it's not entirely >> clear when the function name is the same as the mnemonic of an >> instruction that only exists on newer CPUs and the later patch > > There is no RDMSRQ instruction on any x86 CPU. And perhaps wrongly so. On the binutils side I did argue previously that it is in the spirit of the original AT&T assembler language to permit, but not require, suffixes matching the size of (uniform) register operands. Even for insns not allowing for memory operands, simply for overall consistency. (I took the liberty to at least limit the number of Cc-ed lists some.) Jan