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[175.34.62.5]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23de4285d7asm36020595ad.29.2025.07.10.21.43.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 10 Jul 2025 21:43:08 -0700 (PDT) Message-ID: Date: Fri, 11 Jul 2025 14:43:03 +1000 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/3] arm64: cacheinfo: Provide helper to compress MPIDR value into u32 To: James Morse , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Greg Kroah-Hartman , "Rafael J . Wysocki" , sudeep.holla@arm.com, Rob Herring , Ben Horgan , Jonathan Cameron , Catalin Marinas , WillDeaconwill@kernel.org References: <20250704173826.13025-1-james.morse@arm.com> <20250704173826.13025-4-james.morse@arm.com> Content-Language: en-US From: Gavin Shan In-Reply-To: <20250704173826.13025-4-james.morse@arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 7/5/25 3:38 AM, James Morse wrote: > Filesystems like resctrl use the cache-id exposed via sysfs to identify > groups of CPUs. The value is also used for PCIe cache steering tags. On > DT platforms cache-id is not something that is described in the > device-tree, but instead generated from the smallest MPIDR of the CPUs > associated with that cache. The cache-id exposed to user-space has > historically been 32 bits. > > MPIDR values may be larger than 32 bits. > > MPIDR only has 32 bits worth of affinity data, but the aff3 field lives > above 32bits. The corresponding lower bits are masked out by > MPIDR_HWID_BITMASK and contain an SMT flag and Uni-Processor flag. > > Swizzzle the aff3 field into the bottom 32 bits and using that. > > In case more affinity fields are added in the future, the upper RES0 > area should be checked. Returning a value greater than 32 bits from > this helper will cause the caller to give up on allocating cache-ids. > > Signed-off-by: James Morse > Reviewed-by: Jonathan Cameron > --- > Changes since v1: > * Removal of unrelated changes. > * Added a comment about how the RES0 bit safety net works. > --- > arch/arm64/include/asm/cache.h | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > Reviewed-by: Gavin Shan