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Wed, 24 Jun 2026 09:00:55 +0000 Message-ID: Date: Wed, 24 Jun 2026 17:00:45 +0800 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 6/6] x86/resctrl: Add support for L3 occupancy monitoring via RMID MMIO read To: Reinette Chatre CC: , , , , , , , , , , , , , References: <21beef1acbba4bc7bbc6e54dc11868116638d5b5.1781332698.git.yu.c.chen@intel.com> <04f67dbd-43ed-4863-a51f-cf75e9a02e55@intel.com> <166a4a2e-e2de-46ed-a854-d81d4f7a197c@intel.com> <1308bfd9-e2e8-4dc5-9847-fbb99f177477@intel.com> Content-Language: en-US From: "Chen, Yu C" In-Reply-To: <1308bfd9-e2e8-4dc5-9847-fbb99f177477@intel.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: SI1PR02CA0031.apcprd02.prod.outlook.com (2603:1096:4:1f6::11) To DM4PR11MB6020.namprd11.prod.outlook.com (2603:10b6:8:61::19) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM4PR11MB6020:EE_|SJ0PR11MB5150:EE_ X-MS-Office365-Filtering-Correlation-Id: ed1660e3-ec02-4bd1-9463-08ded1cf19b2 X-LD-Processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|366016|1800799024|23010399003|22082099003|18002099003|3023799007|4143699003|56012099006|11063799006|6133799003; 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>>>>>>      bool erdt_enabled(void); >>>>>> +struct rdt_domain_hdr; >>>>>> +int erdt_mon_read(struct rdt_domain_hdr *hdr, int ev_id, int rmid, u64 *val); >>>>>>      DECLARE_PER_CPU(struct resctrl_pqr_state, pqr_state); >>>>>>    diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c >>>>>> index 90730f0851fa..fe812f7190fc 100644 >>>>>> --- a/arch/x86/kernel/cpu/resctrl/core.c >>>>>> +++ b/arch/x86/kernel/cpu/resctrl/core.c >>>>>> @@ -965,7 +965,7 @@ static __init bool get_rdt_mon_resources(void) >>>>>>        bool ret = false; >>>>>>          if (rdt_cpu_has(X86_FEATURE_CQM_OCCUP_LLC)) { >>>>>> -        resctrl_enable_mon_event(QOS_L3_OCCUP_EVENT_ID, false, 0, NULL); >>>>>> +        resctrl_enable_mon_event(QOS_L3_OCCUP_EVENT_ID, erdt_enabled(), 0, NULL); >>>>>>            ret = true; >>>>>>        } >>>>>>        if (rdt_cpu_has(X86_FEATURE_CQM_MBM_TOTAL)) { >>>>> >>>>> As mentioned in patch #1, when erdt_enabled() is true the enumeration still proceeds to >>>>> enumerate the monitoring properties via CPUID to discover the number of RMIDs that the >>>>> *MSR* supports and use it as the maximum RMID (and thus the maximum number of registers) >>>>> that MMIO supports? >>>>> >>>> >>>> OK, will switch to the maximum RMID exposed by ACPI table, if erdt_enabled() is true. >>> >>> I believe the issue is larger than just the RMID enumeration. The CPUID and ACPI enumeration >>> appears to be fully intertwined. Taking a closer look at what above code does: >>> it checks *CPUID* whether CMT is enabled and then enables the LLC occupancy event to blindly use >>> MMIO if ERDT is enabled, irrespective of whether the ERDT tables include a cache monitoring table >>> or not. How is it guaranteed that if ERDT is enabled that there is a cache monitoring table? >>> Should it not be the existence of the ACPI cache monitoring table and its properties that >>> determines whether the LLC occupancy counter using MMIO registers should be enabled? >>> >> >> I see. How about replacing erdt_enabled() with fine-grained helper functions such as >> erdt_has_cmrc(), erdt_has_mmrc(), and erdt_has_marc()? The latter two will be added >> later for region-aware MBM/MBA. CMRC, MMRC and MARC are not guaranteed to coexist, >> so splitting them into separate helpers would offer finer control. > I am concerned where this is headed since it looks to me as though the plan is to > sprinkle these finer grained checks throughout resctrl. The erdt_has_* helper functions would ideally live under arch/x86/kernel/cpu/resctrl/ rather than the generic fs/resctrl directory, as architecture-specific code in the former path is allow to see erdt logic I suppose? That said, since there are a large number of such routines, introduce a dedicated helper to handle this uniformly would be better(using arch_priv) > To me this sounds complicated > and error prone. Consider that resctrl_enable_mon_event() has an arch_priv parameter. To me > this seems to be the appropriate place for the architecture to give itself the needed > information about how to read the event. > OK, if I understand correctly, we can use the following logic to hide erdt from monitor read: /* * helper to get the erdt's monitor arch_priv, * defined in erdt.c, NULL in other place. * * caller doesn't know about CMRC */ void *get_evt_priv(enum resctrl_event_id eventid) { if (!erdt_enabled()) return NULL; switch (eventid) { case QOS_L3_OCCUP_EVENT_ID: return cmrc_priv_valid ? &cmrc_priv : NULL; default: return NULL; } } arch/x86/kernel/cpu/resctrl/core.c get_rdt_mon_resources(): if (rdt_cpu_has(X86_FEATURE_CQM_OCCUP_LLC)) { void *priv = get_evt_priv(QOS_L3_OCCUP_EVENT_ID); resctrl_enable_mon_event(QOS_L3_OCCUP_EVENT_ID, priv != NULL, 0, priv); } arch/x86/kernel/cpu/resctrl/monitor.c resctrl_arch_rmid_read(): if (arch_priv) return erdt_mon_read(hdr, eventid, rmid, val); return arch_l3_read_event(hdr, rmid, eventid, val, r); So in this way, there is no event-type checks in the read path. Adding MMRC later only extends the switch in get_evt_priv(). thanks, Chenyu