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Tue, 29 Mar 2022 03:01:13 -0700 (PDT) Received: from [192.168.1.145] ([207.188.167.132]) by smtp.gmail.com with ESMTPSA id v1-20020adf9e41000000b00205c3d212easm4214242wre.51.2022.03.29.03.01.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 29 Mar 2022 03:01:12 -0700 (PDT) Message-ID: Date: Tue, 29 Mar 2022 12:01:11 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH v4 17/22] arm64: dts: mt8192: Add dpi node Content-Language: en-US To: "allen-kh.cheng" , Rob Herring , Krzysztof Kozlowski Cc: Project_Global_Chrome_Upstream_Group@mediatek.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, Chen-Yu Tsai , Ryder Lee , Hui Liu References: <20220318144534.17996-1-allen-kh.cheng@mediatek.com> <20220318144534.17996-18-allen-kh.cheng@mediatek.com> <019b1a59-7531-75cf-3b86-d2798ca9823a@gmail.com> From: Matthias Brugger In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 29/03/2022 09:45, allen-kh.cheng wrote: > Hi Matthias, > > On Fri, 2022-03-25 at 16:24 +0100, Matthias Brugger wrote: >> >> On 18/03/2022 15:45, Allen-KH Cheng wrote: >>> Add dpi node for mt8192 SoC. >>> >>> Signed-off-by: Allen-KH Cheng >>> --- >>> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++ >>> 1 file changed, 11 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi >>> b/arch/arm64/boot/dts/mediatek/mt8192.dtsi >>> index 71ad3adeed51..a77d405dd508 100644 >>> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi >>> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi >>> @@ -1236,6 +1236,17 @@ >>> power-domains = <&spm >>> MT8192_POWER_DOMAIN_DISP>; >>> }; >>> >>> + dpi0: dpi@14016000 { >>> + compatible = "mediatek,mt8192-dpi"; >>> + reg = <0 0x14016000 0 0x1000>; >>> + interrupts = >> 0>; >>> + clocks = <&mmsys CLK_MM_DPI_DPI0>, >>> + <&mmsys CLK_MM_DISP_DPI0>, >>> + <&apmixedsys CLK_APMIXED_TVDPLL>; >>> + clock-names = "pixel", "engine", "pll"; >>> + status = "disabled"; >> >> We are missing the output port node here. >> >> Regards, >> Matthias >> > > We will add output port in mt8192-asurada.dtsi (inlude mt8192.dtsi) for > board level. > Got it, patch now applied. > Do we need to add any futher information in binding? > Hm, probably we should mark the output port as optional? Can you check how other bindings manage that? Thanks, Matthias > Thanks, > Allen > >>> + }; >>> + >>> iommu0: m4u@1401d000 { >>> compatible = "mediatek,mt8192-m4u"; >>> reg = <0 0x1401d000 0 0x1000>; >