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Mon, 29 Jun 2026 02:20:44 -0700 (PDT) X-Received: by 2002:ac8:7f13:0:b0:51a:8c9b:64a5 with SMTP id d75a77b69052e-51a8c9b9539mr87798951cf.9.1782724843963; Mon, 29 Jun 2026 02:20:43 -0700 (PDT) Received: from [192.168.120.170] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c11fbbaa46asm745789766b.10.2026.06.29.02.20.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 29 Jun 2026 02:20:43 -0700 (PDT) Message-ID: Date: Mon, 29 Jun 2026 11:20:40 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC v4 1/9] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add glymur-qmp-gen5x8-pcie-phy compatible To: Qiang Yu Cc: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260518-link_mode_0519-v4-0-269cd73cc5d1@oss.qualcomm.com> <20260518-link_mode_0519-v4-1-269cd73cc5d1@oss.qualcomm.com> <5dffdbe0-cbb9-429e-ba15-0afdf6f20fba@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYwNjI5MDA3NCBTYWx0ZWRfX80sn4br+kSeY EHxJ2b2jqfFIVFWEVej482jIDglTgOvpix1SuskArR444REtKTU1Yf2rwIoNXcY6teKEbqOfrTT R6m77mCykKB5sfK3LWcC2LXWXoor+iE= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjI5MDA3NCBTYWx0ZWRfXxQQKDKhLbZHt 2PkPARytcGeEwzuifoOFR7UE+dp2lfZHGxetwUToaA4RG9O01s0//KCJvGBBWZxXTOlHp3PFmYQ VcMNTtwMisWxZNJb5QH3z2H8AILDS4o5DyVZfoimdsxq3AhWu7ADFg70ynRSUGU6fEUvpl8BMvS ojR2LIkxVA/wuXcnJeDcMAUU+17hzj6yKIWhVakfLZO+AHyR46s4LLX58X8QOaqySicl4GzjQS/ 4MhdeqHi94EAsKtj4GuuaTP/ux5KxUiY2EdMhnKLPvz8mYDcCcPERP59D10Hi3VB04MQ33osK2S eUtk7edH24Qw2C3vo+mFgGkv+L19TCQ30eH3651rZDTgim2CGqPQIn628Bf+26ZHpY9N1WEgQUa wadUn1aaSV1beE09/klPzl4L+773HTWiwwsz4hFq6/LPyEkFOPBmuG9xJsU9H7t9c0ywqj7z0IK y2jjUdybDiwR5vbnWDQ== X-Proofpoint-GUID: OYsiNuKx3E40vKxneIUmdLQoI3ZQr4bW X-Authority-Analysis: v=2.4 cv=cefiaHDM c=1 sm=1 tr=0 ts=6a4238ed cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=p_8c1NbHuTntNjfAQcgA:9 a=QEXdDO2ut3YA:10 a=kacYvNCVWA4VmyqE58fU:22 X-Proofpoint-ORIG-GUID: OYsiNuKx3E40vKxneIUmdLQoI3ZQr4bW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-29_02,2026-06-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 lowpriorityscore=0 malwarescore=0 bulkscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 adultscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606290074 On 6/29/26 7:14 AM, Qiang Yu wrote: > On Tue, Jun 16, 2026 at 04:03:39PM +0200, Konrad Dybcio wrote: >> On 5/19/26 7:47 AM, Qiang Yu wrote: >>> The Glymur SoC uses a single PCIe Gen5 PHY hardware block for the >>> PCIe3a/PCIe3b controllers. This block supports two link modes: >>> >>> 1. x4+x4: two 4-lane PHY instances are exposed >>> 2. x8: one 8-lane PHY instance is exposed >>> >>> Add qcom,glymur-qmp-gen5x8-pcie-phy as a multi-mode PHY compatible and >>> document the new link-mode property, which selects the active link mode >>> via a TCSR syscon register. >>> >>> Document the required clocks, resets, and power-domains for both PHY >>> instances active in x8 mode. Use #phy-cells = <1> for this compatible, >>> where the cell value is the PHY index within the active link mode. >>> >>> Signed-off-by: Qiang Yu >>> --- >> >> [...] >> >>> @@ -68,20 +69,29 @@ properties: >>> - const: ref >>> - enum: [rchng, refgen] >>> - const: pipe >>> - - const: pipediv2 >>> + - enum: [pipediv2, phy_b_aux] >> >> I'm surprised to learn 3A doesnm'doesn't have a PIPE_DIV2 clk.. it does have >> a non-div2 one though. >> >> Seems like it's specifically not the case on Hamoa and Makena, so perhaps >> it's better for maintainability if the Glymur list was separate >> > Do you mean splitting Glymur out into a separate YAML file for the PCIe3 > PHY? I'll add a new file if that's preferred and Krzysztof is on board. I believe that may be the better approach since Glymur seems to be an outlier with the clocks I mentioned above. Krzysztof? Konrad