From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12ED21E49F for ; Mon, 23 Feb 2026 13:02:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771851723; cv=none; b=PJFGQtsR+tpIy8iZSp/Tj/zvSLWtXK5Azi+/Q2+hWa4hrxUrw7tx6YmqIniNGRt9FnGXalFpQa39L4U9a+yxcP+87ae5Pnzcrgzrqxn77sC04+U/0FwZLU9x6sx22dwTUf+J/9Bwg3Kq9ZnpyOr8yY44Fj2b1FEdPy3MtjuxQM8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771851723; c=relaxed/simple; bh=uty3zD22JbjBsQ+Hol0jnFAoRmj262IBujSXOGhaqG0=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=rC0Yb8seg7a9Iyf3x0Oe/8Vcqsem5ZLXxZJI+vwVoz0nGNp9amwXnFBgiUDPlkMrNPpl4Z58VIsMQVUzh89VRqKA0apOxZOdGFE09JUlDHQhT+G7HsDW7EpHj9UDVZD9oyyTGsblHmnhxDapk1to3lZX54Nik85PCsY37WA9fpk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=cg4pvRYN; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="cg4pvRYN" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 41205C116C6; Mon, 23 Feb 2026 13:01:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1771851722; bh=uty3zD22JbjBsQ+Hol0jnFAoRmj262IBujSXOGhaqG0=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=cg4pvRYN/PneO0ZuQ2YEt6S07AB1iVEyGwdOwjUG12NppCtClxN/K5TI5eU/g/XlU wl3U14eFnstmcFS+P30wJUNka+2y7ntRS/aolCXbTmV2hqgiCQm6kzA3FtGjAM+Afm C3e9fBA8VHZGjSJ5LTURTZC297efhP7BqeBEASOElZW1ngkY4kM6AXSXxXbuDNBv8E ekS/QIcNgQKCxuCz9xQ/b9l8gZ7LiIO9Rh+NK9M1PzxI07tDuHG3/Z2PYCXFvutful c3xTzrNUIjID/q/w9Gm6RfxYPTgI3Q/4zui7oVQ2HcCPFFztXblatEv6W5AqjWsCw9 TTV1uyJV8nrLQ== Message-ID: Date: Mon, 23 Feb 2026 14:01:53 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [LSF/MM/BPF TOPIC] Per-process page size To: Pedro Falcato , Dev Jain Cc: lsf-pc@lists.linux-foundation.org, ryan.roberts@arm.com, catalin.marinas@arm.com, will@kernel.org, ardb@kernel.org, willy@infradead.org, hughd@google.com, baolin.wang@linux.alibaba.com, akpm@linux-foundation.org, lorenzo.stoakes@oracle.com, Liam.Howlett@oracle.com, vbabka@suse.cz, rppt@kernel.org, surenb@google.com, mhocko@suse.com, linux-mm@kvack.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20260217145026.3880286-1-dev.jain@arm.com> From: "David Hildenbrand (Arm)" Content-Language: en-US Autocrypt: addr=david@kernel.org; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 2/23/26 13:49, Pedro Falcato wrote: > On Mon, Feb 23, 2026 at 10:37:55AM +0530, Dev Jain wrote: >>> I don't understand. What exactly are you trying to do here? Maintain 2 >>> different paging structures, one for core mm and the other for the arch? As >>> done in architectures with no radix tree paging structures? >> >> The mm->pgd will be the software pagetable. So suppose that do_anonymous_page is >> doing set_ptes on the PTE table belonging to the software pagetable. We will >> hook a "native_set_ptes" into set_ptes, which will set the ptes on a different >> pagetable maintained by arm64 code (probably mm_context_t->native_pgd). > > Traditionally, you do this kind of funky manipulation in update_mmu_cache. > > But this is still an extremely complex and invasive change (that I assume most > people would not like to see) with dubious benefit. > >> >>> >>> If so, that's wildly inefficient, unless you're willing to go into reclaimable >>> page tables on the arm64 side. And that brings extra problems and extra fun :) >> >> I didn't understand the reclaimable reference, but yes we need to make this efficient. > > I'm not talking about CPU runtime efficiency, but memory efficiency. Doing > this makes you essentially duplicate page tables - not exactly ideal. This is > a Known Problem in classic UNIX systems which do something similar > (but not the same): anonymous memory pointers are stored in some intermediary > structure (SunOS and UVM call it "amap"), and paging structures are entirely > redundant there. They can freely tear down a page table because they can freely > put it together from the amap and file mappings (what they call vm_object and > we call address_space). > > Anyway, I'm boring you with these funny historical details so you can understand > the similarities: the Linux page table format generally matches hardware, and > we store anonymous memory "state" there, so you can't ever tear-down a pgtable > without losing state of whatever was mapped there before. However, if you go > down the "arm64 now has a separate pgtable structure", the roles switch: > arm64's internal page table format makes for the real page tables, and linux's > pgtable structure is nothing more than an "amap". So you could (and perhaps > should) freely reclaim arm64 MMU page tables once memory pressure hits, because > they are freely discardable. > > Does this make sense? I've been thinking about building the 64k page tables similar to how HMM/KVM handles it, invalidating them through mmu notifiers etc and building them on demand. Considering the 64k MMU of a process just like a special device that builds its own page tables. This way, they could get reclaimed more easily and most of the core + arm64 page able manipulation code could be kept as is. However, I don't know how much the performance impact of that approach would be. -- Cheers, David