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bh=oncd5AKdpggnAPxxh4VFHdLCR4iA8DGRcyLR55yh0uA=; b=ah9OUxbvTxwLRRpbUEo1SKuhnKzm7zxXDAoj7QYcIMLmq53pMMRl3goiDleP1f8m7dDV1C3haimrbrojX0kfMKHgS4ITOBIX/Zxl2aPHJbkHOTi3a4e0VDoBrfGyLvxzIMpXOiWY+Dzq5DwAOaZzc4l0BYaAPte29iWyce+7euc= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=wolfvision.net; Received: from GVXPR08MB11763.eurprd08.prod.outlook.com (2603:10a6:150:313::16) by GV2PR08MB8320.eurprd08.prod.outlook.com (2603:10a6:150:b5::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.139.11; Wed, 17 Jun 2026 16:20:21 +0000 Received: from GVXPR08MB11763.eurprd08.prod.outlook.com ([fe80::8790:5e3:beb2:5bc6]) by GVXPR08MB11763.eurprd08.prod.outlook.com ([fe80::8790:5e3:beb2:5bc6%5]) with mapi id 15.21.0113.015; Wed, 17 Jun 2026 16:20:21 +0000 Message-ID: Date: Wed, 17 Jun 2026 18:20:19 +0200 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/3] dt-bindings: phy: rockchip-inno-csi-dphy: add rockchip,clk-lane-phase property To: Conor Dooley Cc: Vinod Koul , Neil Armstrong , Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <20260617-feature-mipi-csi-dphy-4k60-v1-0-4611ff00b0ff@wolfvision.net> <20260617-feature-mipi-csi-dphy-4k60-v1-2-4611ff00b0ff@wolfvision.net> <20260617-deviate-sulk-c57104ef939f@spud> From: Gerald Loacker Organization: WolfVision GmbH In-Reply-To: <20260617-deviate-sulk-c57104ef939f@spud> Content-Type: text/plain; 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The hardware default is 3. > > Can this instead become rockchip,clk-lane-phase-ps and be listed in the > actual unit? > With the -ps suffix, you can then drop the $ref. > The default should be listed as "default: 3" (or default: 120) > > pw-bot: changes-requested > Thanks for the suggestion. The phase setting is a hardware tap index (0–7) selecting a delay line position. The datasheet mentions “about 40 ps” per step, but this is not a calibrated or guaranteed value and may vary with PVT. Because of that, I’d prefer to keep the property as an index and document the approximate delay in the description: Clock lane sampling phase selection (hardware tap index 0–7). Each step corresponds to an approximately 40 ps delay as described in the hardware specification. This matches the hardware model more closely. Happy to adjust if needed. >> + >> required: >> - compatible >> - reg >> >> -- >> 2.34.1 >>