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Thu, 10 Apr 2025 09:14:00 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 53A9E0sA024266 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 10 Apr 2025 09:14:00 GMT Received: from [10.218.7.247] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 10 Apr 2025 02:13:55 -0700 Message-ID: Date: Thu, 10 Apr 2025 14:43:52 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V2 2/6] phy: qcom-qmp-ufs: Refactor phy_power_on and phy_calibrate callbacks To: , , , , , , CC: , , , , , Can Guo References: <20250318144944.19749-1-quic_nitirawa@quicinc.com> <20250318144944.19749-3-quic_nitirawa@quicinc.com> Content-Language: en-US From: Nitin Rawat In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Ia17VMEn0O_RUNO79BLfP3RTUNvzsWg4 X-Proofpoint-GUID: Ia17VMEn0O_RUNO79BLfP3RTUNvzsWg4 X-Authority-Analysis: v=2.4 cv=NaLm13D4 c=1 sm=1 tr=0 ts=67f78bd8 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=KKAkSRfTAAAA:8 a=COk6AnOGAAAA:8 a=RY7zYqXbgaIDV70ltDMA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=cvBusfyB2V15izCimMoJ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-10_01,2025-04-08_04,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 impostorscore=0 priorityscore=1501 adultscore=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 mlxlogscore=999 clxscore=1015 phishscore=0 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504100068 On 3/18/2025 8:39 PM, neil.armstrong@linaro.org wrote: > On 18/03/2025 15:49, Nitin Rawat wrote: >> Commit 052553af6a31 ("ufs/phy: qcom: Refactor to use phy_init call") >> puts enabling regulators & clks, calibrating UFS PHY, starting serdes >> and polling PCS ready status into phy_power_on. >> >> In Current code regulators enable, clks enable, calibrating UFS PHY, >> start_serdes and polling PCS_ready_status are part of phy_power_on. >> >> UFS PHY registers are retained after power collapse, meaning calibrating >> UFS PHY, start_serdes and polling PCS_ready_status can be done only when >> hba is powered_on, and not needed every time when phy_power_on is called >> during resume. Hence keep the code which enables PHY's regulators & clks >> in phy_power_on and move the rest steps into phy_calibrate function. >> >> Refactor the code to retain PHY regulators & clks in phy_power_on and >> move out rest of the code to new phy_calibrate function. >> >> Co-developed-by: Can Guo >> Signed-off-by: Can Guo >> Signed-off-by: Nitin Rawat >> --- >>   drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 18 ++---------------- >>   1 file changed, 2 insertions(+), 16 deletions(-) >> >> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/ >> qualcomm/phy-qcom-qmp-ufs.c >> index bb836bc0f736..0089ee80f852 100644 >> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c >> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c >> @@ -1796,7 +1796,7 @@ static int qmp_ufs_com_exit(struct qmp_ufs *qmp) >>       return 0; >>   } >> >> -static int qmp_ufs_init(struct phy *phy) >> +static int qmp_ufs_power_on(struct phy *phy) >>   { >>       struct qmp_ufs *qmp = phy_get_drvdata(phy); >>       const struct qmp_phy_cfg *cfg = qmp->cfg; >> @@ -1898,21 +1898,6 @@ static int qmp_ufs_exit(struct phy *phy) >>       return 0; >>   } >> >> -static int qmp_ufs_power_on(struct phy *phy) >> -{ >> -    int ret; >> - >> -    ret = qmp_ufs_init(phy); >> -    if (ret) >> -        return ret; >> - >> -    ret = qmp_ufs_phy_calibrate(phy); >> -    if (ret) >> -        qmp_ufs_exit(phy); >> - >> -    return ret; >> -} >> - >>   static int qmp_ufs_disable(struct phy *phy) >>   { >>       int ret; >> @@ -1942,6 +1927,7 @@ static int qmp_ufs_set_mode(struct phy *phy, >> enum phy_mode mode, int submode) >>   static const struct phy_ops qcom_qmp_ufs_phy_ops = { >>       .power_on    = qmp_ufs_power_on, >>       .power_off    = qmp_ufs_disable, >> +    .calibrate    = qmp_ufs_phy_calibrate, > > Ok so this will break the UFS until patch 5 is applied, > breaking bisectability. > > Make sure UFS host driver calls calibrate first, and then > do the refactor in the PHY driver. Hi Neil. Thanks for the review. I have taken care of bisecatablity compliance by making UFS host driver calls calibrate first in latest patch set. Regards, Nitin > > And either all would go in a single tree or either PHY > or SCSI maintainer would need to provide an immutable > branch for the final merge. > >>       .set_mode    = qmp_ufs_set_mode, >>       .owner        = THIS_MODULE, >>   }; >> -- >> 2.48.1 >> >> >