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[188.86.219.160]) by smtp.gmail.com with ESMTPSA id p12sm724836wrr.10.2021.11.17.09.41.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 17 Nov 2021 09:41:47 -0800 (PST) Message-ID: Date: Wed, 17 Nov 2021 18:41:46 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.2.0 Subject: Re: [PATCH v3] PCI: mediatek-gen3: Disable DVFSRC voltage request Content-Language: en-US To: Jianjun Wang , Lorenzo Pieralisi , Rob Herring , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Bjorn Helgaas , Ryder Lee Cc: linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, qizhong.cheng@mediatek.com, Ryan-JH.Yu@mediatek.com, Tzung-Bi Shih References: <20211015063602.29058-1-jianjun.wang@mediatek.com> From: Matthias Brugger In-Reply-To: <20211015063602.29058-1-jianjun.wang@mediatek.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 15/10/2021 08:36, Jianjun Wang wrote: > When the DVFSRC (dynamic voltage and frequency scaling resource collector) > feature is not implemented, the PCIe hardware will assert a voltage request > signal when exit from the L1 PM Substates to request a specific Vcore > voltage, but cannot receive the voltage ready signal, which will cause > the link to fail to exit the L1 PM Substates. > > Disable DVFSRC voltage request by default, we need to find a common way to > enable it in the future. > > Fixes: d3bf75b579b9 ("PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192") > Signed-off-by: Jianjun Wang > Reviewed-by: Tzung-Bi Shih > Tested-by: Qizhong Cheng Reviewed-by: Matthias Brugger > --- > drivers/pci/controller/pcie-mediatek-gen3.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c > index f3aeb8d4eaca..79fb12fca6a9 100644 > --- a/drivers/pci/controller/pcie-mediatek-gen3.c > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c > @@ -79,6 +79,9 @@ > #define PCIE_ICMD_PM_REG 0x198 > #define PCIE_TURN_OFF_LINK BIT(4) > > +#define PCIE_MISC_CTRL_REG 0x348 > +#define PCIE_DISABLE_DVFSRC_VLT_REQ BIT(1) > + > #define PCIE_TRANS_TABLE_BASE_REG 0x800 > #define PCIE_ATR_SRC_ADDR_MSB_OFFSET 0x4 > #define PCIE_ATR_TRSL_ADDR_LSB_OFFSET 0x8 > @@ -297,6 +300,11 @@ static int mtk_pcie_startup_port(struct mtk_pcie_port *port) > val &= ~PCIE_INTX_ENABLE; > writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG); > > + /* Disable DVFSRC voltage request */ > + val = readl_relaxed(port->base + PCIE_MISC_CTRL_REG); > + val |= PCIE_DISABLE_DVFSRC_VLT_REQ; > + writel_relaxed(val, port->base + PCIE_MISC_CTRL_REG); > + > /* Assert all reset signals */ > val = readl_relaxed(port->base + PCIE_RST_CTRL_REG); > val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB; >