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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-60c8292076csm1554764a12.32.2025.06.27.08.09.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 27 Jun 2025 08:09:43 -0700 (PDT) Message-ID: Date: Fri, 27 Jun 2025 17:09:38 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v9 01/10] clk: qcom: clk-alpha-pll: Add support for dynamic update for slewing PLLs To: Taniya Das , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Will Deacon , Catalin Marinas Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20250612-qcs615-mm-v9-clock-controllers-v9-0-b34dc78d6e1b@quicinc.com> <20250612-qcs615-mm-v9-clock-controllers-v9-1-b34dc78d6e1b@quicinc.com> <9a9d84e3-49de-4fbd-9c0d-180e3e498125@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <9a9d84e3-49de-4fbd-9c0d-180e3e498125@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjI3MDEyMiBTYWx0ZWRfX5qpleQn67+TE p67J95hJFnZT5MXNGnH1NPm90NJ+1Ob1mSGjCV1xh6xZBfCs987YID9YrAeleVoAeFQ6tZuH6/4 bsA1FQ/6AWgcVIUQdc83mGmtttitRBd9LyJQtrVGr3Lg5gMUTqeon14fWHwHvOhrJxkkmcGuzoG B3DO3ZBBwyGqxkAWqXR/E66HVPMxwEp2cnJ45ATXP3oT4kUhrKU6+8XIxUMtaDuiN2a/8nxKt3S 94ucij8Ul1F69Z/OrNXt67Kb+MCXXq8S4PGFt6PWxoOZC6pkWRmPHr5s/HkL982thHYfdshMA1r E1k12r0QIASv3HwosgRiTjWdx0ek3+awoR1zb86wlINgBRqQhGcLsvilHY4qoDRZCo6ZPSfxlb2 9jMIVwsc5uCbTdHHpGH2zHoW06qlLWZR10mlQHVYypCl8fOZc0v0esK+jlZ6IuNOR1VP3egN X-Authority-Analysis: v=2.4 cv=XPQwSRhE c=1 sm=1 tr=0 ts=685eb43a cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=6IFa9wvqVegA:10 a=COk6AnOGAAAA:8 a=Wx9hSxQhFZ4lEN4NqugA:9 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: RP5jFuafqSy9LXrnWc9Xx1K8IN-bRxZ9 X-Proofpoint-ORIG-GUID: RP5jFuafqSy9LXrnWc9Xx1K8IN-bRxZ9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-06-27_04,2025-06-26_05,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 suspectscore=0 mlxscore=0 spamscore=0 phishscore=0 malwarescore=0 mlxlogscore=999 bulkscore=0 priorityscore=1501 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506270122 On 6/25/25 12:31 PM, Taniya Das wrote: > > > On 6/15/2025 12:20 AM, Konrad Dybcio wrote: >> On 6/12/25 11:55 AM, Taniya Das wrote: >>> The alpha PLLs which slew to a new frequency at runtime would require >>> the PLL to calibrate at the mid point of the VCO. Add the new PLL ops >>> which can support the slewing of the PLL to a new frequency. >>> >>> Reviewed-by: Imran Shaik >>> Signed-off-by: Taniya Das >>> --- [...] >>> + regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); >>> + regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), lower_32_bits(a)); >>> + regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), upper_32_bits(a)); >>> + >>> + /* Ensure that the write above goes before slewing the PLL */ >>> + mb(); >> >> Here however, the write may not arrive at the clock controller before you >> proceed to slew_update() >> > > Yes, it is required here and will keep it. You should change it to a readback instead Konrad