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Mon, 26 Oct 2026 05:21:29 -0700 (PDT) Received: from [10.204.78.119] ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c46bd64cd1dsm306573566b.45.2026.10.26.05.21.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 26 Oct 2026 05:21:28 -0700 (PDT) Message-ID: Date: Mon, 26 Oct 2026 17:51:19 +0530 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 05/11] phy: qualcomm: qmp-combo: Add hardware-specific dp_aux_cfg2 and dp_phy_cfg1 fields To: Konrad Dybcio , Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Dmitry Baryshkov , Wesley Cheng , Abel Vesa , Johan Hovold , Bjorn Andersson , Dmitry Baryshkov Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Ritesh Kumar , Mahadevan P References: <20261001-glymur-phy-v3-v5-0-3848c2615d5a@oss.qualcomm.com> <20261001-glymur-phy-v3-v5-5-3848c2615d5a@oss.qualcomm.com> Content-Language: en-GB From: Nabige Aala In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=G7GJgNk5 c=1 sm=1 tr=0 ts=6adf45cb cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=z9__apPl9ExnX2lTgnYA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-ORIG-GUID: kFolPr6HISZiC8PvPhvgZ6i_W3J-xQES X-Proofpoint-Spam-Info: AW1haW4tMjYxMDI2MDA0OSBTYWx0ZWRfX7hT4A6kg7uKq aGbppnpXSVm4S71LnULcx6F4qHpb1eBzTDOA0RbOV2xwcfEPUEMHygVCbw6H4P1ZSlQSJbsMHRp 8gkcTRflz6EhCm6LRLJ5uX6ySbOKkPs= X-Proofpoint-GUID: kFolPr6HISZiC8PvPhvgZ6i_W3J-xQES X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDI2MDA0OSBTYWx0ZWRfXztSkz9nGLUoJ IldYVMVDk2b61ZdhQ/0ecnRTjU/c8ITKLl8NVLj7pZapbNjGJr2XLqeLT/xBMhSI9RtlaQT/qV0 3oC7AyJyaPj2SBHgGsxw6pfRCNH60WIujTgWacDEuxni4+cl8C3JWxfiKZMgXM/yTutwlzcZdvW bwHJ6eCgBDXd6KmFI2rkBp+h1Pc02cuG83e8vZe3B3ANh+u84HGpWIGxHTad/TbJuranbYYHwLK GGyuxDqWZoXlTrUzsmlYsB5VjNGNiapLFO6Vo8WsTLlKEjbin7vq3SgWRqHpF5in5wkqDpi9haW B4ZA1kwZ5aLGXU11raus7Dmt5UPVrOpC6EAsWEXeD4/4zOpY61w1CkUivYoM7DAEy/NpGxoEQ6r nhfW2Jlx4BcOwN7ATWxvSmcEzvRt8OumCqUGlWyp63RLZl1VERUTpC8oQniLoSevxo1SJzzjZyx TMEZQLbh4/q1OIozUIg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-26_02,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 phishscore=0 spamscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610260049 On 10/22/2026 4:04 PM, Konrad Dybcio wrote: > On 10/1/26 11:34 AM, Nabige Aala wrote: >> From: Ritesh Kumar >> >> Add dp_aux_cfg2 and dp_phy_cfg1 fields to qmp_phy_cfg to allow >> hardware-specific DP PHY register values to be specified per-platform >> rather than hardcoded in the configure functions. >> >> Define named constants QSERDES_DP_PHY_AUX_CFG2_V456/V8 and >> QSERDES_DP_PHY_CFG1_V456/V8 for better readability and maintainability. >> >> Populate the new fields in all existing DP PHY cfg structures: >> - V456-based platforms (sar2130p, sc8180x, sc8280xp, x1e80100, sm8250, >> sm8350, sm8475, sm8550, sm8650, sm8750) use V456 constants >> - Glymur (V8) uses V8 constants >> >> Signed-off-by: Ritesh Kumar >> Signed-off-by: Mahadevan P >> Signed-off-by: Nabige Aala >> --- >> drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 37 ++++++++++++++++++++++++++++++- >> 1 file changed, 36 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c >> index 646e97a52886..ebe2e6136f7a 100644 >> --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c >> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c >> @@ -2486,6 +2486,14 @@ static const struct qmp_combo_lane_mapping dp_data_lanes[] = { >> >> struct qmp_combo; >> >> +/* DP PHY AUX_CFG2 register values for different hardware versions */ >> +#define QSERDES_DP_PHY_AUX_CFG2_V456 0xa4 >> +#define QSERDES_DP_PHY_AUX_CFG2_V8 0x06 > The doc says this should be 0x16 for flipped typec Thank you for the review, Konrad. After checking the hardware documentation more carefully, AUX_CFG2 depend upon the swap_sel, which does not indicate the Type-C orientation. Its value depends on the SoC hardware configuration — specifically how the AUX lines are physically wired on the board. So tying AUX_CFG2 to TYPEC_ORIENTATION_REVERSE would be incorrect. I also tested the approach you suggested, where different AUX_CFG2 values are programmed based on the cable orientation. However, with that change, link training fails consistently. Thanks, Nabige > >> +/* DP PHY CFG_1 register values for different hardware versions */ >> +#define QSERDES_DP_PHY_CFG1_V456 0x0f >> +#define QSERDES_DP_PHY_CFG1_V8 0x2f > And this should reportedly be 0x13/0x53 for normal/flipped > > Konrad