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The system > PLL - PLLA and the system PLL divided by 2 - PLLADIV2 with PLL ID 0 and > 4 respectively, both have a hardware divider /2. This has to be taken into > account in the software to obtain the right frequencies. Support for the > same is added in the PLL driver. > > fcorepllack -----> HW Div = 2 -+--> fpllack > | > +--> HW Div = 2 ---> fplladiv2ck > > In this case the corepll freq is 1600 MHz. So, the plla freq is 800 MHz > after the hardware divider and the plladiv2 freq is 400 MHz after the > hardware divider (given that the DIVPMC is 0). > > Signed-off-by: Varshini Rajendran Reviewed-by: Claudiu Beznea > --- > Changes in v5: > - Corrected typos in commit message. > - Rewrote the conditional statement. > --- > drivers/clk/at91/clk-sam9x60-pll.c | 30 ++++++++++++++++++++++++++++-- > drivers/clk/at91/pmc.h | 1 + > 2 files changed, 29 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c > index b0314dfd7393..fda041102224 100644 > --- a/drivers/clk/at91/clk-sam9x60-pll.c > +++ b/drivers/clk/at91/clk-sam9x60-pll.c > @@ -73,9 +73,15 @@ static unsigned long sam9x60_frac_pll_recalc_rate(struct clk_hw *hw, > { > struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); > struct sam9x60_frac *frac = to_sam9x60_frac(core); > + unsigned long freq; > > - return parent_rate * (frac->mul + 1) + > + freq = parent_rate * (frac->mul + 1) + > DIV_ROUND_CLOSEST_ULL((u64)parent_rate * frac->frac, (1 << 22)); > + > + if (core->layout->div2) > + freq >>= 1; > + > + return freq; > } > > static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core) > @@ -432,6 +438,12 @@ static unsigned long sam9x60_div_pll_recalc_rate(struct clk_hw *hw, > return DIV_ROUND_CLOSEST_ULL(parent_rate, (div->div + 1)); > } > > +static unsigned long sam9x60_fixed_div_pll_recalc_rate(struct clk_hw *hw, > + unsigned long parent_rate) > +{ > + return parent_rate >> 1; > +} > + > static long sam9x60_div_pll_compute_div(struct sam9x60_pll_core *core, > unsigned long *parent_rate, > unsigned long rate) > @@ -606,6 +618,16 @@ static const struct clk_ops sam9x60_div_pll_ops_chg = { > .restore_context = sam9x60_div_pll_restore_context, > }; > > +static const struct clk_ops sam9x60_fixed_div_pll_ops = { > + .prepare = sam9x60_div_pll_prepare, > + .unprepare = sam9x60_div_pll_unprepare, > + .is_prepared = sam9x60_div_pll_is_prepared, > + .recalc_rate = sam9x60_fixed_div_pll_recalc_rate, > + .round_rate = sam9x60_div_pll_round_rate, > + .save_context = sam9x60_div_pll_save_context, > + .restore_context = sam9x60_div_pll_restore_context, > +}; > + > struct clk_hw * __init > sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, > const char *name, const char *parent_name, > @@ -725,10 +747,14 @@ sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock, > else > init.parent_names = &parent_name; > init.num_parents = 1; > - if (flags & CLK_SET_RATE_GATE) > + > + if (layout->div2) > + init.ops = &sam9x60_fixed_div_pll_ops; > + else if (flags & CLK_SET_RATE_GATE) > init.ops = &sam9x60_div_pll_ops; > else > init.ops = &sam9x60_div_pll_ops_chg; > + > init.flags = flags; > > div->core.id = id; > diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h > index bb9da35198d9..91d1c6305d95 100644 > --- a/drivers/clk/at91/pmc.h > +++ b/drivers/clk/at91/pmc.h > @@ -64,6 +64,7 @@ struct clk_pll_layout { > u8 frac_shift; > u8 div_shift; > u8 endiv_shift; > + u8 div2; > }; > > extern const struct clk_pll_layout at91rm9200_pll_layout;