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Mon, 19 Oct 2026 23:52:54 -0700 (PDT) Received: from [192.168.226.26] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6b38a1e9db0sm4984385a12.33.2026.10.19.23.52.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 19 Oct 2026 23:52:54 -0700 (PDT) Message-ID: Date: Tue, 20 Oct 2026 08:52:49 +0200 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 05/10] clk: qcom: cpu-8996: move off the ACD leg while the PLL speeds up To: Dmitry Baryshkov , Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Joonwoo Park , Imran Khan , Rajendra Nayak , Jeffrey Hugo , Maxime Ripard , Vikash Garodia , Dikshita Agarwal , Bryan O'Donoghue , Mauro Carvalho Chehab , Ilia Lin , Loic Poulain , Konrad Dybcio , Yassine Oudjana , Dmitry Baryshkov , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, Christopher Obbard References: <20261019-msm8998-fix-clocks-v1-0-370949e4d8a0@oss.qualcomm.com> <20261019-msm8998-fix-clocks-v1-5-370949e4d8a0@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20261019-msm8998-fix-clocks-v1-5-370949e4d8a0@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: rhZrMlxU1nsuHSPrgOSeKcxvh4Suul3N X-Proofpoint-ORIG-GUID: rhZrMlxU1nsuHSPrgOSeKcxvh4Suul3N X-Authority-Analysis: v=2.4 cv=L7qI0OT8 c=1 sm=1 tr=0 ts=6ad70fc8 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=-GkAsrVB-0cJHUZqiU8A:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIwMDAyNyBTYWx0ZWRfX2G/pkHT8rRjj 1lJrguArPcu4ihSUVm9fahTWZncJyz6oNlP8h5TGZqUVDIBAAtxPFqYYpnOr4A8ujAUwi/m8ER3 FuauXyyUvc+x2wWkVanj+saoneJdKpFRBrTL9h0AAaCc3rVSNbLEyOiPimAm2/Jl3g8+jPWZn7T 5FrW92jwpDIC5FLZYO2L0Ss+pgZEdvg6Myvn0yPAkT0hNfJBDzsVBYw4Mbb7U8yxYq/IW9/djb2 C/hI9MQVR1/N6fdxWxfXfTxI3yFpmLkOg5x+lVH9LwAz/2YMk3FTxQGdu+85DoH82Nbp/WYDRJK CR0BjrJgmUKeB+6DsQANJatqLalyWztzMAxm/JrLFl0o8ae3HvZ1TSt2BnzSlc/PNxaWa1ZRbMz MUY8oT/H4eelcFq0WaX73EqyCRR4C0qs2JfZZFYSV9+42VaqFfeGZl14AIkDShMd7CoRuuI/m94 OEI8uqAj3uXSoqOIYsQ== X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIwMDAyNyBTYWx0ZWRfX5ZZ57G2HDA0Y jOxzEFC+54+UbAm68drc6KDpDjy190sTL09nMbuokbJU/PAcWgov3GxuIJwlkLUM6Wngd3o7+1o WWMb8KAYois1BOl+/gtyFz33INjchDY= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-20_01,2026-10-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 adultscore=0 phishscore=0 priorityscore=1501 bulkscore=0 malwarescore=0 suspectscore=0 spamscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610200027 On 10/19/26 3:41 PM, Dmitry Baryshkov wrote: > The MSM8996 CPU clusters sometimes run at half the rate they report > after going up between two frequencies above 600 MHz, and stay there > until the cluster drops below 600 MHz. The PLL, the muxes and the rest > of the cluster clock registers are all as expected: it is the ACD that > latches at half the rate when the PLL is reprogrammed to a higher rate > underneath it, and selecting the ACD leg again clears it. The driver > only moves off the ACD leg when going below 600 MHz. > > Like the vendor kernel, run from PLL/2 while the PLL goes up and return > to the ACD leg afterwards. Point the SMUX at PLL/2 at probe time instead > of XO, so that the cluster does not drop to 19.2 MHz on the first such > switch. > > Fixes: 03e342dc45c9 ("clk: qcom: Add CPU clock driver for msm8996") > Reported-by: Christopher Obbard > Signed-off-by: Dmitry Baryshkov > --- LLM has the following comments: For old rates above 1190.4 MHz the SMUX output is old/2, which exceeds MAX_PLL_MAIN_FREQ (595.2 MHz). Downstream does not do this. clock-cpu-8996.c acd_safe_freq() returns freq/2 only up to 1190.4 MHz and MAX_PLL_MAIN_FREQ above that, and pre_set_rate() retunes the PLL to that value before the increase. The comment there says the main output is what keeps voltage constraints satisfied, which implies a 595.2 MHz limit on that output. Up to 1190.4 MHz the two approaches are equivalent: both move the cluster off the ACD leg and run it from the non-ACD path at half the old rate. Above that they diverge. Either clamp the SMUX choice to match acd_safe_freq(), or explain why old/2 is safe above 1190.4 MHz. The second needs the hardware limit for the non-ACD output, which is not in the patch or the cover letter. Konrad