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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b972e18e238sm54861266b.48.2026.03.11.06.18.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Mar 2026 06:18:52 -0700 (PDT) Message-ID: Date: Wed, 11 Mar 2026 14:18:49 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/2] i2c: qcom-cci: Add DT property for SCL clock stretching To: Loic Poulain , ckeitz@amazon.com, Mukesh Kumar Savaliya Cc: Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260305-cci-scl-stretch-v1-0-8412abc65745@amazon.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: Jlv7zrpxghfr4jWs0YvG1cGBP-98CAZV X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzExMDExMiBTYWx0ZWRfX+4XYntwW5c/P 05dKpB9chCc1AXUs3rbIAS1gtnVQZa7i2ojTy3liUUM0SE97+uqmdwKcc17nFBwlDbRYWH1tFvh z+8Vnq2T5H3vOM/1xjGkDDLao6qxjklNIxENEr/HwpIGdeOpAArLEaG5Wu0R2nyDbdFQYc4KZ1H +JaslU8eIRvolCHHmblTdXcV7X3WrP/ZbALrjfnNa4UZJ8LlBgldQAXxaQTTUByRwwY2rTiPsOr 3tEpPj5sT9+tCdT4lCofSL99zLgsxARRUNzZcxcnNM3zBX5nInK6Dl7HYPUaA4yjT9rl+Nf+UXI MyRqkSOoABo8UqiKO9PUcN6dF6hERRfIS7zOkELrdMzzIk6ip/lRsqbxW4OK/+Jy+yhTkvyOSHs EUtTEj2L8z7XKMptou91xdD3+evs0bggkAQJEAnNibNBL9C/9/5XOOJtSE1rW5dlZ4eme+l8k8K q1HDSR7jnYqrr1Ty8kA== X-Proofpoint-ORIG-GUID: Jlv7zrpxghfr4jWs0YvG1cGBP-98CAZV X-Authority-Analysis: v=2.4 cv=TtLrRTXh c=1 sm=1 tr=0 ts=69b16bc3 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=VwQbUJbxAAAA:8 a=p0SCdqENNPgbPqcv8GAA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-11_01,2026-03-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 bulkscore=0 adultscore=0 impostorscore=0 lowpriorityscore=0 malwarescore=0 clxscore=1015 suspectscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603110112 On 3/5/26 4:16 PM, Loic Poulain wrote: > Hi Cory, > > On Thu, Mar 5, 2026 at 3:40 PM Cory Keitz via B4 Relay > wrote: >> >> The Qualcomm CCI I2C controller has an SCL clock stretch enable bit in >> the MISC_CTL register. Currently the driver hardcodes this off in >> per-SoC hw_params tables, with no way to enable it from the device tree >> on a per-master basis. >> >> Clock stretching is required for GMSL configurations where the >> deserializer uses it to absorb the latency imposed by forwarding I2C >> transactions across the serial link. Without it, the CCI master exhibits >> intermittent transaction failure. >> >> This series adds a "qcom,scl-stretch-enable" boolean DT property to >> individual CCI i2c-bus sub-nodes. The property ORs with the existing >> hw_params default so it is purely additive and does not affect masters >> that do not set it. >> >> Tested on sa8775p using the qcom,sm8250-cci compatible string with two >> CCI buses connected to one max96724/max96717 GMSL2 pair each. Enabling >> this property eliminated intermittent NACK errors during serializer >> and/or deserializer probe. > > I'm not convinced this kind of hardware behaviour belongs in > devicetree. As far as I understand, clock stretching is part of the > I2C specification, and slaves are allowed to use it whenever they need > additional time. Masters are therefore expected to tolerate > stretching. Given that, why not enable it unconditionally in the > driver? Is there any downside to doing so? +Mukesh may be able to help Konrad