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([2001:b07:6468:f312:5e2c:eb9a:a8b6:fd3e]) by smtp.gmail.com with ESMTPSA id d3sm31485720wrp.79.2021.02.08.02.31.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 08 Feb 2021 02:31:38 -0800 (PST) Subject: Re: [PATCH v2 4/4] KVM: x86: Expose Architectural LBR CPUID and its XSAVES bit To: "Xu, Like" , Sean Christopherson Cc: Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Like Xu References: <20210203135714.318356-1-like.xu@linux.intel.com> <20210203135714.318356-5-like.xu@linux.intel.com> <8321d54b-173b-722b-ddce-df2f9bd7abc4@redhat.com> <219d869b-0eeb-9e52-ea99-3444c6ab16a3@intel.com> <7698fd6c-94da-e352-193f-e09e002a8961@redhat.com> <6f733543-200e-9ddd-240b-1f956a003ed6@intel.com> From: Paolo Bonzini Message-ID: Date: Mon, 8 Feb 2021 11:31:36 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <6f733543-200e-9ddd-240b-1f956a003ed6@intel.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 07/02/21 02:02, Xu, Like wrote: > On 2021/2/5 19:00, Paolo Bonzini wrote: >> On 05/02/21 09:16, Xu, Like wrote: >>> Hi Paolo, >>> >>> I am wondering if it is acceptable for you to >>> review the minor Architecture LBR patch set without XSAVES for v5.12 ? >>> >>> As far as I know, the guest Arch LBR  can still work without XSAVES >>> support. >> >> I dopn't think it can work.  You could have two guests on the same >> physical CPU and the MSRs would be corrupted if the guests write to >> the MSR but they do not enable the LBRs. >> >> Paolo >> > Neither Arch LBR nor the old version of LBR have this corruption issue, > and we will not use XSAVES for at least LBR MSRs in the VMX transaction. > > This is because we have reused the LBR save/restore swicth support from the > host perf mechanism in the legacy LBR support, which will save/restore > the LBR > MSRs of the vcpu (thread) when the vcpu is sched in/out. > > Therefore, if we have two guests on the same physical CPU, the usage of > LBR MSRs > is isolated, and it's also true when we use LBR to trace the hypervisor > on the host. > The same thing happens on the platforms which supports Arch LBR. > > I propose that we don't support using XSAVES to save/restore Arch LRB > *in the guest* > (just like the guest Intel PT), but use the traditional RD/WRMSR, which > still works > like the legacy LBR. Ok, this makes sense. I'll review the patches more carefully, looking at 5.13 for the target. Paolo > Since we already have legacy LBR support, we can add a small amount of > effort (just > two more MSRs emulation and related CPUID exposure) to support Arch LBR > w/o XSAVES. > > I estimate that there are many issues we need to address when we > supporting guests > to use xsaves instructions. As a rational choice, we could enable the > basic Arch LBR. > > Paolo and Sean, what do you think ? > > --- > thx, likexu >