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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-81fa1277a15sm1121763b3a.42.2026.01.15.22.40.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 15 Jan 2026 22:40:45 -0800 (PST) Message-ID: Date: Fri, 16 Jan 2026 12:10:40 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 3/4] arm64: dts: qcom: Introduce Glymur base dtsi To: Konrad Dybcio , Bjorn Andersson Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jyothi Kumar Seerapu , Maulik Shah , Sibi Sankar , Taniya Das , Kamal Wadhwa , Qiang Yu , Manaf Meethalavalappu Pallikunhi , Jishnu Prakash , Abel Vesa References: <20260112-upstream_v3_glymur_introduction-v4-0-8a0366210e02@oss.qualcomm.com> <20260112-upstream_v3_glymur_introduction-v4-3-8a0366210e02@oss.qualcomm.com> <5cd1f4f5-808d-46cf-a44a-ee5428987727@oss.qualcomm.com> Content-Language: en-US From: Pankaj Patil In-Reply-To: <5cd1f4f5-808d-46cf-a44a-ee5428987727@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTE2MDA1MiBTYWx0ZWRfX6J1HX25XFjnm kErkOD5zfVEBTM6meIw/8rYvwpvW95kFs3dqhcEdWvUfFAP6xzAzpb/EBOCG61EN1HHVByHJNWB UXas6BVHzRJ8y4fqZjXYKMBApkSFuWsGHH/bGRJB84UQP55HJjqkx/M4QUpVVvsZavuBiBJEhxI OTdumn5G7dhEoBaPnUAIGTvnSbOs+OEzGjScQCi/7AhHrPlA4bWZ99+1q9FbyzNNheevqjyzdVk ntgF9zodvNFxaIdPfQh6lR61uv6VSM+rOUb3jc9JNEe7ZIuxaFglJssj+oPn3FWl1QX+1n9WaYA MIiL78vK5qQ8yRcgYZPRrb2g8FeUrB3HQ3ng7/HQmIN9cX6XLga6qg2/P71fEAJtHBGnFgYVy76 TP17YDmqyaARZnDVv2TQLdUeUotYGuW3HYCAVlj0L5U7biTz/3I34gqOyQIHCnqkQznXSpdooF5 9wdaGuTW1UegJQnIrzQ== X-Authority-Analysis: v=2.4 cv=Sv6dKfO0 c=1 sm=1 tr=0 ts=6969dd6f cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=5tyqGv89VatObklNbhcA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-GUID: Yg0Eaq9csvUOLRgQCyVhqYLa3hInJyb2 X-Proofpoint-ORIG-GUID: Yg0Eaq9csvUOLRgQCyVhqYLa3hInJyb2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-16_02,2026-01-15_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 impostorscore=0 bulkscore=0 adultscore=0 phishscore=0 spamscore=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601160052 On 1/14/2026 7:17 PM, Konrad Dybcio wrote: > On 1/14/26 11:29 AM, Pankaj Patil wrote: >> On 1/14/2026 9:47 AM, Bjorn Andersson wrote: >>> On Mon, Jan 12, 2026 at 05:52:36PM +0530, Pankaj Patil wrote: >>>> Introduce the base device tree support for Glymur – Qualcomm's >>>> next-generation compute SoC. The new glymur.dtsi describes the core SoC >>>> components, including: >>>> >>>> - CPUs and CPU topology >>>> - Interrupt controller and TLMM >>>> - GCC,DISPCC and RPMHCC clock controllers >>>> - Reserved memory and interconnects >>>> - APPS and PCIe SMMU and firmware SCM >>>> - Watchdog, RPMHPD, APPS RSC and SRAM >>>> - PSCI and PMU nodes >>>> - QUPv3 serial engines >>>> - CPU power domains and idle states, plus SCMI/ SRAM pieces for CPU DVFS >>>> - PDP0 mailbox, IPCC and AOSS >>>> - Display clock controller >>>> - SPMI PMIC arbiter with SPMI0/1/2 buses >>>> - SMP2P nodes >>>> - TSENS and thermal zones (8 instances, 92 sensors) >>>> >>>> Add dtsi files for PMH0101, PMK8850, PMCX0102, SMB2370, PMH0104, >>>> PMH0110 along with temp-alarm and GPIO nodes needed on Glymur >>>> >>>> Enabled PCIe controllers and associated PHY to support boot to >>>> shell with nvme storage, >>>> List of PCIe instances enabled: >>>> >>>> - PCIe3b >>>> - PCIe4 >>>> - PCIe5 >>>> - PCIe6 >>>> >>> >>> Why didn't you run "make qcom/glymur-crd.dtb CHECK_DTBS=1" before >>> sending patches to the mailing list?! >>> >>> It would taken you 30 seconds to conclude that I can't do anything with >>> these patches. >>> >>> Regards, >>> Bjorn >> >> I've ran the bindings check, dt-bindings specified as dependencies will fix the errors >> Additionally, I'll drop qup-memory from interconnects for serial and spi in next rev, >> which cause the bindings errors, this was missed > > The SPI flavor of QUPs is definitely DMA-capable and I don't see how it > could error out with the current bindings definition > > Konrad Yes, only serial nodes will error out, will drop for serial/uart nodes