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([2a09:80c0:192:0:20af:34be:985b:b6c8]) by smtp.gmail.com with ESMTPSA id g13-20020a05600c4ecd00b0038a0165f2fbsm4412271wmq.17.2022.03.17.03.04.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 17 Mar 2022 03:04:19 -0700 (PDT) Message-ID: Date: Thu, 17 Mar 2022 11:04:18 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.6.2 Content-Language: en-US To: Catalin Marinas Cc: linux-kernel@vger.kernel.org, Andrew Morton , Hugh Dickins , Linus Torvalds , David Rientjes , Shakeel Butt , John Hubbard , Jason Gunthorpe , Mike Kravetz , Mike Rapoport , Yang Shi , "Kirill A . Shutemov" , Matthew Wilcox , Vlastimil Babka , Jann Horn , Michal Hocko , Nadav Amit , Rik van Riel , Roman Gushchin , Andrea Arcangeli , Peter Xu , Donald Dutile , Christoph Hellwig , Oleg Nesterov , Jan Kara , Liang Zhang , Pedro Gomes , Oded Gabbay , Will Deacon , Michael Ellerman , Benjamin Herrenschmidt , Paul Mackerras , Heiko Carstens , Vasily Gorbik , Alexander Gordeev , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , linux-mm@kvack.org, x86@kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org References: <20220315141837.137118-1-david@redhat.com> <20220315141837.137118-5-david@redhat.com> From: David Hildenbrand Organization: Red Hat Subject: Re: [PATCH v1 4/7] arm64/pgtable: support __HAVE_ARCH_PTE_SWP_EXCLUSIVE In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 16.03.22 19:27, Catalin Marinas wrote: > On Tue, Mar 15, 2022 at 03:18:34PM +0100, David Hildenbrand wrote: >> diff --git a/arch/arm64/include/asm/pgtable-prot.h b/arch/arm64/include/asm/pgtable-prot.h >> index b1e1b74d993c..62e0ebeed720 100644 >> --- a/arch/arm64/include/asm/pgtable-prot.h >> +++ b/arch/arm64/include/asm/pgtable-prot.h >> @@ -14,6 +14,7 @@ >> * Software defined PTE bits definition. >> */ >> #define PTE_WRITE (PTE_DBM) /* same as DBM (51) */ >> +#define PTE_SWP_EXCLUSIVE (_AT(pteval_t, 1) << 2) /* only for swp ptes */ > > I think we can use bit 1 here. > >> @@ -909,12 +925,13 @@ static inline pmd_t pmdp_establish(struct vm_area_struct *vma, >> /* >> * Encode and decode a swap entry: >> * bits 0-1: present (must be zero) >> - * bits 2-7: swap type >> + * bits 2: remember PG_anon_exclusive >> + * bits 3-7: swap type >> * bits 8-57: swap offset >> * bit 58: PTE_PROT_NONE (must be zero) > > I don't remember exactly why we reserved bits 0 and 1 when, from the > hardware perspective, it's sufficient for bit 0 to be 0 and the whole > pte becomes invalid. We use bit 1 as the 'table' bit (when 0 at pmd > level, it's a huge page) but we shouldn't check for this on a swap > entry. You mean arch/arm64/include/asm/pgtable-hwdef.h:#define PTE_TABLE_BIT (_AT(pteval_t, 1) << 1) right? I wonder why it even exists, for arm64 I only spot: arch/arm64/include/asm/pgtable.h:#define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) I don't really see code that sets PTE_TABLE_BIT. Similarly, I don't see code that sets PMD_TABLE_BIT/PUD_TABLE_BIT/P4D_TABLE_BIT. Most probably setting code is not using the defines, that's why I'm not finding it. -- Thanks, David / dhildenb