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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b040a410817sm1034669266b.101.2025.09.03.08.14.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 03 Sep 2025 08:14:32 -0700 (PDT) Message-ID: Date: Wed, 3 Sep 2025 17:14:29 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 3/6] arm64: dts: qcom: sa8775p: Add gpu and gmu nodes To: Dmitry Baryshkov Cc: Akhil P Oommen , Sean Paul , Konrad Dybcio , Abhinav Kumar , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Connor Abbott , Srinivas Kandagatla , Rob Clark , Dmitry Baryshkov , Gaurav Kohli , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Puranam V G Tejaswi References: <20250822-a663-gpu-support-v4-0-97d26bb2144e@oss.qualcomm.com> <20250822-a663-gpu-support-v4-3-97d26bb2144e@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: XY1Vm_AF3NJF8WLERFrUzHSiHDtk5Wpv X-Authority-Analysis: v=2.4 cv=Jt/xrN4C c=1 sm=1 tr=0 ts=68b85b5b cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=dNECfGFYMPGvbPEIsa0A:9 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 a=TjNXssC_j7lpFel5tvFf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: XY1Vm_AF3NJF8WLERFrUzHSiHDtk5Wpv X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODMwMDAwMSBTYWx0ZWRfXyFswnaSipHU2 BEJ99FDG7QK0DXiJ3U6QCVzDKK6zZWMxv29b8lt8peYK7OjVziUnIcLfuR+SwrGf14f8Gwd6nf9 V6leNmHqsE8hDG0iQguhF4yfYa2G7S8kRY6ms9kdOmk0MTPjenVRi6VG+oKnYYFZsMxq8jpTEhZ uFwJ86c5uhSck5VoW2M054+cA4KuoTWK1Vb4ganxtA0MW7YQmpXUXuIrOnO/UYXzxpKLYARPc6N sFd8l/E6XU0BNjWKDOOmtpYCWvyul90LivdwuozB2sIoWAkFaqv+dGb9emCcwIOihjUNHU4UEiO X4ZYPWd4u7jRwQi+bLiTt7edxoQ40veu3EovyfytBdx+Waqkd4WTDPUadkja++BzMKh2z0KjjNi kkQB5Upy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-03_08,2025-08-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 clxscore=1015 bulkscore=0 impostorscore=0 spamscore=0 phishscore=0 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508300001 On 9/3/25 4:00 PM, Dmitry Baryshkov wrote: > On Wed, Sep 03, 2025 at 03:36:34PM +0200, Konrad Dybcio wrote: >> On 9/3/25 2:39 PM, Dmitry Baryshkov wrote: >>> On Wed, Sep 03, 2025 at 02:26:30PM +0200, Konrad Dybcio wrote: >>>> On 8/21/25 8:55 PM, Akhil P Oommen wrote: >>>>> From: Puranam V G Tejaswi >>>>> >>>>> Add gpu and gmu nodes for sa8775p chipset. As of now all >>>>> SKUs have the same GPU fmax, so there is no requirement of >>>>> speed bin support. >>>>> >>>>> Signed-off-by: Puranam V G Tejaswi >>>>> Signed-off-by: Akhil P Oommen >>>>> Reviewed-by: Dmitry Baryshkov >>>>> --- >>>>> arch/arm64/boot/dts/qcom/lemans.dtsi | 116 +++++++++++++++++++++++++++++++++++ >>>>> 1 file changed, 116 insertions(+) >>>>> >>>>> diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi >>>>> index 8ceb59742a9fc6562b2c38731ddabe3a549f7f35..8eac8d4719db9230105ad93ac22287850b6b007c 100644 >>>>> --- a/arch/arm64/boot/dts/qcom/lemans.dtsi >>>>> +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi >>>>> @@ -1097,6 +1097,18 @@ ipcc: mailbox@408000 { >>>>> #mbox-cells = <2>; >>>>> }; >>>>> >>>>> + qfprom: efuse@784000 { >>>>> + compatible = "qcom,sa8775p-qfprom", "qcom,qfprom"; >>>>> + reg = <0x0 0x00784000 0x0 0x2410>; >>>> >>>> len = 0x3000 >>>> >>>> [...] >>>> >>>>> + gmu: gmu@3d6a000 { >>>>> + compatible = "qcom,adreno-gmu-663.0", "qcom,adreno-gmu"; >>>>> + reg = <0x0 0x03d6a000 0x0 0x34000>, >>>> >>>> This bleeds into GPU_CC, len should be 0x26000 >>> >>> gpucc is in the middle of GMU, see other platforms. >> >> This is not the case here > > Why? I think GPU CC is a part of the GMU by design: GMU accesses GPU CC > registers directly from the firmware. Correct, however this is only a similarly sounding argument - the DT describes the hardware from the main Arm cluster POV. The GMU Cortex-M core has its own address map etc. Konrad