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Peter Anvin" , x86@kernel.org, Borislav Petkov , Dave Hansen Date: Wed, 30 Oct 2024 17:25:44 -0400 In-Reply-To: References: <20240906221824.491834-1-mlevitsk@redhat.com> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.36.5 (3.36.5-2.fc32) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 7bit On Wed, 2024-10-30 at 14:22 -0700, Sean Christopherson wrote: > On Wed, Oct 30, 2024, Maxim Levitsky wrote: > > On Fri, 2024-09-06 at 18:18 -0400, Maxim Levitsky wrote: > > > Recently we came up upon a failure where likely the guest writes > > > 0xff4547ceb1600000 to MSR_KERNEL_GS_BASE and later on, qemu > > > sets this value via KVM_PUT_MSRS, and is rejected by the > > > kernel, likely due to not being canonical in 4 level paging. > > > > > > One of the way to trigger this is to make the guest enter SMM, > > > which causes paging to be disabled, which SMM bios re-enables > > > but not the whole 5 level. MSR_KERNEL_GS_BASE on the other > > > hand continues to contain old value. > > > > > > I did some reverse engineering and to my surprise I found out > > > that both Intel and AMD indeed ignore CR4.LA57 when doing > > > canonical checks on this and other msrs and/or other arch > > > registers (like GDT base) which contain linear addresses. > > > > > > V2: addressed a very good feedback from Chao Gao. Thanks! > > > > > > V3: also fix the nested VMX, and also fix the > > > MSR_IA32_SYSENTER_EIP / MSR_IA32_SYSENTER_ESP > > > > > > V4: > > > - added PT and PEBS msrs > > > - corrected emulation of SGDT/SIDT/STR/SLDT instructions > > > - corrected canonical checks for TLB invalidation instructions > > > > > > Best regards, > > > Maxim Levitsky > > > > > > Maxim Levitsky (4): > > > KVM: x86: drop x86.h include from cpuid.h > > > KVM: x86: implement emul_is_noncanonical_address using > > > is_noncanonical_address > > > KVM: x86: model canonical checks more precisely > > > KVM: nVMX: fix canonical check of vmcs12 HOST_RIP > > > > > > arch/x86/kvm/cpuid.h | 1 - > > > arch/x86/kvm/emulate.c | 15 ++++++----- > > > arch/x86/kvm/kvm_emulate.h | 5 ++++ > > > arch/x86/kvm/mmu.h | 1 + > > > arch/x86/kvm/mmu/mmu.c | 2 +- > > > arch/x86/kvm/vmx/hyperv.c | 1 + > > > arch/x86/kvm/vmx/nested.c | 35 +++++++++++++++++--------- > > > arch/x86/kvm/vmx/pmu_intel.c | 2 +- > > > arch/x86/kvm/vmx/sgx.c | 5 ++-- > > > arch/x86/kvm/vmx/vmx.c | 4 +-- > > > arch/x86/kvm/x86.c | 13 +++++++--- > > > arch/x86/kvm/x86.h | 49 ++++++++++++++++++++++++++++++++++-- > > > 12 files changed, 102 insertions(+), 31 deletions(-) > > > > > > -- > > > 2.26.3 > > > > > > > > > > Hi, > > A very gentle ping on this patch series. > > Heh, good timing, I literally (like, 2 seconds ago) applied this (still need to > test before you'll see a "thank you" email). > Thank you! Best regards, Maxim Levitsky