From: "H. Peter Anvin" <hpa@zytor.com>
To: Yuhong Bao <yuhongbao_386@hotmail.com>, kees.cook@canonical.com
Cc: x86@kernel.org, linux-kernel@vger.kernel.org, tglx@linutronix.de,
mingo@redhat.com, tabbott@ksplice.com, sam@ravnborg.org,
heukelum@fastmail.fm
Subject: RE: [PATCH] x86: clear XD_DISABLED flag on Intel to regain NX
Date: Thu, 17 Jun 2010 20:03:48 -0700 [thread overview]
Message-ID: <c426f516-7a1c-49bd-a05e-da98171f1c5a@email.android.com> (raw)
In-Reply-To: <SNT125-W601D37A89A8CBFFDFFF40EC3C00@phx.gbl>
Yes, I mentally flipped the sense of the bit... talked to Kees already.
"Yuhong Bao" <yuhongbao_386@hotmail.com> wrote:
>
>> a) Not all Intel CPUs with extended CPUID levels have
>> MSR_IA32_MISC_ENABLE bit 34. Since we can't take traps here we would
>> have to know positively that we aren't going to trip on anything.
>It won't as these older Intel CPUs are always going to read this bit as zero, and even if no checking for this is include all the wrmsr would do is write the same value back, which won't cause a trap.
>
>Yuhong Bao
>
>_________________________________________________________________
>Hotmail has tools for the New Busy. Search, chat and e-mail from your inbox.
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prev parent reply other threads:[~2010-06-18 3:04 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-06-17 22:13 Kees Cook
2010-06-17 22:27 ` H. Peter Anvin
2010-06-18 2:07 ` Yuhong Bao
2010-06-18 3:03 ` H. Peter Anvin [this message]
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