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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9e565df86esm291855266b.112.2024.11.02.02.36.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 02 Nov 2024 02:36:08 -0700 (PDT) Message-ID: Date: Sat, 2 Nov 2024 10:36:04 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/5] arm64: dts: qcom: Add base sm8750 dtsi and mtp and qrd dts To: Melody Olvera , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Catalin Marinas , Will Deacon , Geert Uytterhoeven , Dmitry Baryshkov , AngeloGioacchino Del Regno , Neil Armstrong , Arnd Bergmann , =?UTF-8?Q?N=C3=ADcolas_F_=2E_R_=2E_A_=2E_Prado?= , Stephen Boyd , Trilok Soni , Satya Durga Srinivasu Prabhala Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Taniya Das , Jishnu Prakash , Raviteja Laggyshetty References: <20241021232114.2636083-1-quic_molvera@quicinc.com> <20241021232114.2636083-5-quic_molvera@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20241021232114.2636083-5-quic_molvera@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: fym9Hf_Ho1sZEDZfcrjud5gSuqNKxdsi X-Proofpoint-ORIG-GUID: fym9Hf_Ho1sZEDZfcrjud5gSuqNKxdsi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1015 impostorscore=0 bulkscore=0 lowpriorityscore=0 mlxlogscore=999 malwarescore=0 priorityscore=1501 suspectscore=0 mlxscore=0 spamscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411020085 On 22.10.2024 1:21 AM, Melody Olvera wrote: > Add base dtsi for the sm8750 SoC describing the CPUs, GCC and > RPMHCC clock controllers, geni UART, interrupt controller, TLMM, > reserved memory, interconnects, regulator, and SMMU nodes. Also add > MTP and QRD board dts files for sm8750. > > Co-developed-by: Taniya Das > Signed-off-by: Taniya Das > Co-developed-by: Jishnu Prakash > Signed-off-by: Jishnu Prakash > Co-developed-by: Raviteja Laggyshetty > Signed-off-by: Raviteja Laggyshetty > Signed-off-by: Melody Olvera > --- [...] > +&spmi_bus { > + pm8550ve_d: pmic@3 { These usually go to a separate file each.. But I see why that would be difficult here. Lately I've been a fan of -pmics.dtsi. WDYT, Bjorn? [...] > + apps_smmu: iommu@15000000 { > + compatible = "qcom,sm8750-smmu-500", "qcom,smmu-500", "arm,mmu-500"; > + reg = <0x0 0x15000000 0x0 0x100000>; > + [...] > + #iommu-cells = <2>; > + #global-interrupts = <1>; This is usually dma-coherent, you can determine that through a smoke test > + }; > + > + intc: interrupt-controller@16000000 { > + compatible = "arm,gic-v3"; > + reg = <0x0 0x16000000 0x0 0x10000>, /* GICD */ > + <0x0 0x16080000 0x0 0x200000>; /* GICR * 12 */ These comments are copypasted gen to gen and don't bring much information atop what's in bindings Konrad