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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b885b6fc4c5sm621398766b.40.2026.01.26.02.31.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 26 Jan 2026 02:31:11 -0800 (PST) Message-ID: Date: Mon, 26 Jan 2026 11:31:09 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] interconnect: qcom: glymur: Add Mahua SoC support To: Dmitry Baryshkov , Raviteja Laggyshetty Cc: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Odelu Kukatla References: <20260123-mahua_icc-v1-0-bc82cb087f1e@oss.qualcomm.com> <20260123-mahua_icc-v1-2-bc82cb087f1e@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTI2MDA4OSBTYWx0ZWRfX/dWnjnQBkYKM 4x5/kz9jQ0rrBV6P4vCUF8boPC+RCrRSklrtn3cCOm3EUrFNaohhbP3Cc9knrNl1rLz9mQFQuL2 19nIP5iVXuM7ZEApue8rEDKX5yKM85mwtBku0QMLWQIl1kv4iO9Pp/wdkQrZ1GFFyVkrgJnLUmf iuqisG3O9eNII4DY7djgOIoxQd5YQvjdvaM0QalJ5PAjik41iLp2hbdMNB57YE8Nuk7Rqe7HLMa rvo5rYKPK+tLIkLY/TpYc3dQ+uBTo/IUPq471vgYrQLPs0bpy+UELhqeAsClQNQOUsTq77VzuRq ItJbTzWBL4OxmkEff+jrI7eVXGCBSCrXwU3H5tFp7s0a3mYVlBrHlN34i61YCxpsAuTIPzfehUG 9ZIMBmg5kaCb30cEwFjBY4HMQ/0VPT1KLG3vYIPZthkVdCYm+9Xpc/YfjonkQ9GFct6Y/z2ONDY qd7ZC8eKWSy4oFoS0Bw== X-Authority-Analysis: v=2.4 cv=UqRu9uwB c=1 sm=1 tr=0 ts=69774271 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=aHkru73TLWHWJvrfeGIA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-ORIG-GUID: vmacwCwAvSk1NOV9P0IoBXK2ETgoJ8RY X-Proofpoint-GUID: vmacwCwAvSk1NOV9P0IoBXK2ETgoJ8RY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.20,FMLib:17.12.100.49 definitions=2026-01-26_02,2026-01-22_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 suspectscore=0 spamscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 malwarescore=0 bulkscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601260089 On 1/23/26 6:58 PM, Dmitry Baryshkov wrote: > On Fri, Jan 23, 2026 at 05:12:36PM +0000, Raviteja Laggyshetty wrote: >> Mahua is a derivative of the Glymur SoC. This patch extends the > > Documentation/process/submitting-patches.rst, look for 'This patch'. > >> Glymur driver to support Mahua by: >> >> 1. Adding new node definitions for interconnects that differ from Glymur >> (Config NoC, High-Speed Coherent NoC, PCIe West ANOC/Slave NoC). >> 2. Reusing existing Glymur definitions for identical NoCs. >> 3. Overriding the channel and buswidth, with Mahua specific values for >> the differing NoCs >> >> Co-developed-by: Odelu Kukatla >> Signed-off-by: Odelu Kukatla >> Signed-off-by: Raviteja Laggyshetty >> --- >> drivers/interconnect/qcom/glymur.c | 153 ++++++++++++++++++++++++++++++++++++- >> 1 file changed, 152 insertions(+), 1 deletion(-) >> >> +static struct qcom_icc_node * const mahua_cnoc_cfg_nodes[] = { > > As you are patching other instances, why can't we just patch out the > PCI_3A out of these structures? > >> >> +static int glymur_qnoc_probe(struct platform_device *pdev) >> +{ >> + if (device_is_compatible(&pdev->dev, "qcom,mahua-mc-virt")) { >> + llcc_mc.channels = 8; >> + ebi.channels = 8; >> + } else if (device_is_compatible(&pdev->dev, "qcom,mahua-hscnoc")) { >> + qns_llcc.channels = 8; >> + chm_apps.channels = 4; >> + qnm_pcie_west.buswidth = 32; >> + } else if (device_is_compatible(&pdev->dev, "qcom,mahua-pcie-west-anoc")) { >> + qns_pcie_west_mem_noc.buswidth = 32; >> + } > > Right here, set the node entries to NULL. +1 Konrad