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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-af91a0761f2sm2392951866b.11.2025.08.13.04.32.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 13 Aug 2025 04:32:22 -0700 (PDT) Message-ID: Date: Wed, 13 Aug 2025 13:32:21 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] spi: spi-qpic-snand: handle 'use_ecc' parameter of qcom_spi_config_cw_read() To: Gabor Juhos , Mark Brown Cc: Md Sadre Alam , Varadarajan Narayanan , Sricharan Ramabadhran , linux-spi@vger.kernel.org, linux-mtd@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250808-qpic-snand-handle-use_ecc-v1-1-67289fbb5e2f@gmail.com> <3e790d99-5c6c-4148-85f5-0023a621afeb@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODEyMDExOSBTYWx0ZWRfX/kAO4t5+2l86 y+dejmtFxYfN9l+84Yw7WnYP74WaUIN0/ZfsrrYu1RsJAnPu1UIghhSXrzZgywD9cwXVoQMDLSy SvOootvgrpVbdGbmAWIZpGYX0mcNQgNO5bTMetzg31H+kHLRpaW/Do9ZvBG8eI1hjhamqkg+lJB 42Ujyh9+7FWEG4vDrDf6NMjSgMBcINKr/n3RxjOLPuh268v9Zth6I1eC5rSZbFtN9f6480Q1TSy E3326KK/Mv1s7DMhDcrbbNWaSu+4h+24GmthPPH9sU7zRJrAU1R2ro/JXOk5PIqk1vC8fZWxM81 Mk1onNvOQIFl5N/70BTMK/qs5kuytd2MuSrVeZpu6/gjBlVhwjCUDMx0yWQ1mC1iSSWg46nQYv9 Vom3eKYW X-Proofpoint-GUID: r8SmQgPlaAo43aQ4HCCLJnZUmRpiKhHM X-Proofpoint-ORIG-GUID: r8SmQgPlaAo43aQ4HCCLJnZUmRpiKhHM X-Authority-Analysis: v=2.4 cv=d4b1yQjE c=1 sm=1 tr=0 ts=689c77c9 cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=pGLkceISAAAA:8 a=EUspDBNiAAAA:8 a=LMlhJLrcAiEsyVNmZoIA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-13_01,2025-08-11_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 spamscore=0 phishscore=0 adultscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508120119 On 8/12/25 1:06 PM, Gabor Juhos wrote: > 2025. 08. 12. 11:55 keltezéssel, Konrad Dybcio írta: >> On 8/8/25 7:15 PM, Gabor Juhos wrote: >>> During raw read, neither the status of the ECC correction nor the erased >>> state of the codeword gets checked by the qcom_spi_read_cw_raw() function, >>> so in case of raw access reading the corresponding registers via DMA is >>> superfluous. >>> >>> Extend the qcom_spi_config_cw_read() function to evaluate the existing >>> (but actually unused) 'use_ecc' parameter, and configure reading only >>> the flash status register when ECC is not used. >>> >>> With the change, the code gets in line with the corresponding part of >>> the config_nand_cw_read() function in the qcom_nandc driver. >>> >>> Signed-off-by: Gabor Juhos >>> --- >>> drivers/spi/spi-qpic-snand.c | 11 ++++++++--- >>> 1 file changed, 8 insertions(+), 3 deletions(-) >>> >>> diff --git a/drivers/spi/spi-qpic-snand.c b/drivers/spi/spi-qpic-snand.c >>> index 7b76d2c82a5287df13ee6fcebc4abbe58ca861ee..119003c4784890458a41c67fa8bc17d721030b0d 100644 >>> --- a/drivers/spi/spi-qpic-snand.c >>> +++ b/drivers/spi/spi-qpic-snand.c >>> @@ -494,9 +494,14 @@ qcom_spi_config_cw_read(struct qcom_nand_controller *snandc, bool use_ecc, int c >>> qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); >>> qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); >>> >>> - qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 2, 0); >>> - qcom_read_reg_dma(snandc, NAND_ERASED_CW_DETECT_STATUS, 1, >>> - NAND_BAM_NEXT_SGL); >>> + if (use_ecc) { >>> + qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 2, 0); >> >> Why are we reading 2 registers (the 2 in the func call) here, ... > > Because when ECC is used, we need the status of the ECC correction from the > NAND_BUFFER_STATUS register which is placed right after the NAND_FLASH_STATUS. > > Here are the relevant definitions from the 'nand-qpic-common.h' header for > reference: > > #define NAND_FLASH_STATUS 0x14 > #define NAND_BUFFER_STATUS 0x18 > > So the two registers can be read with a single DMA operation. > >> ... but 1 everywhere else? > > When ECC is not used, we only need the value from the NAND_FLASH_STATUS > register, so we don't have to read two registers. OK yeah I can see that Reviewed-by: Konrad Dybcio Konrad