From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754682AbcDSO0H (ORCPT ); Tue, 19 Apr 2016 10:26:07 -0400 Received: from mail1.bemta14.messagelabs.com ([193.109.254.107]:20902 "EHLO mail1.bemta14.messagelabs.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752775AbcDSO0F (ORCPT ); Tue, 19 Apr 2016 10:26:05 -0400 X-Greylist: delayed 403 seconds by postgrey-1.27 at vger.kernel.org; Tue, 19 Apr 2016 10:26:04 EDT X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrCIsWRWlGSWpSXmKPExsUSt3OpsW64nVi 4wfKZyhZXLh5ispj68AmbxbcrHUwWl3fNYbPo3NXParHh+1pGBzaPDZ+b2Dx2zrrL7rFpVSeb x763y9g81m+5yuLxeZNcAFsUa2ZeUn5FAmvGordnmApuy1RcPSPdwDhLsouRi0NIYD2jxKLle 9i6GDmBnAqJi++PsoLYvAKZEv9aFzCC2JwC7hKXr/5jhKhxk+icsQXMZhOwkJh84gFYL4uAqs TjE3+ZQGxhgVCJB3umM4MsEBHoYpRY/eoxO0iCWaBc4uymRWwQCwQlTs58wgIRl5A4+OIFM8Q CA4nTCxrB4hIC9hLT318FinMA2foSjcdiIcKGEt9nfWOBCJtLnFlrPoFRcBaSobOQDF3AyLSK Ub04tagstUjXWC+pKDM9oyQ3MTNH19DQRC83tbg4MT01JzGpWC85P3cTIzD0GYBgB+PdPudDj JIcTEqivDzWYuFCfEn5KZUZicUZ8UWlOanFhxhlODiUJHhrbYFygkWp6akVaZk5wCiESUtw8C iJ8IaDpHmLCxJzizPTIVKnGBWlxHnrQRICIImM0jy4NljkX2KUlRLmZQQ6RIinILUoN7MEVf4 VozgHo5IwbwTIFJ7MvBK46a+AFjMBLea/KwqyuCQRISXVwLivTeOuz6K8J9rT7x/77nAn9aBV Wvrt/4xLavssymff8q5m1N0888/m38Jxv3eUPmVs6jsavaRZs2D7cfu9fdt8L6UETn+zSKq+a Vrea+sCebcDLet3bzQNkf+Uvzhict6DzGR3PZ5L+YoKwT+CyjYHrLzKZpqUX5Ybs7r10I6afV 9XLwg4uEeJpTgj0VCLuag4EQD8vufA9wIAAA== X-Env-Sender: Adam.Thomson.Opensource@diasemi.com X-Msg-Ref: server-11.tower-193.messagelabs.com!1461075542!31661916!1 X-Originating-IP: [94.185.165.51] X-StarScan-Received: X-StarScan-Version: 8.28; banners=-,-,- X-VirusChecked: Checked Message-ID: In-Reply-To: References: From: Adam Thomson Date: Tue, 19 Apr 2016 15:19:02 +0100 Subject: [PATCH 1/2] ASoC: da7219: Update PLL ranges and dividers to improve locking To: Mark Brown , Liam Girdwood , Jaroslav Kysela , Takashi Iwai CC: , , Support Opensource MIME-Version: 1.0 Content-Type: text/plain X-KSE-AttachmentFiltering-Interceptor-Info: protection disabled X-KSE-ServerInfo: sw-ex-cashub01.diasemi.com, 9 X-KSE-Antivirus-Interceptor-Info: scan successful X-KSE-Antivirus-Info: Clean, bases: 19/04/2016 09:51:00 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The expected MCLK frequency ranges and the associated dividers are updated to improve PLL locking in a corner scenario, with low MCLK frequency near an input divider change boundary. Signed-off-by: Adam Thomson --- sound/soc/codecs/da7219.c | 28 ++++++++++++++-------------- sound/soc/codecs/da7219.h | 20 ++++++++++---------- 2 files changed, 24 insertions(+), 24 deletions(-) diff --git a/sound/soc/codecs/da7219.c b/sound/soc/codecs/da7219.c index 81c0708..3b1d65b 100644 --- a/sound/soc/codecs/da7219.c +++ b/sound/soc/codecs/da7219.c @@ -1079,21 +1079,21 @@ static int da7219_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, dev_err(codec->dev, "PLL input clock %d below valid range\n", da7219->mclk_rate); return -EINVAL; - } else if (da7219->mclk_rate <= 5000000) { - indiv_bits = DA7219_PLL_INDIV_2_5_MHZ; - indiv = DA7219_PLL_INDIV_2_5_MHZ_VAL; - } else if (da7219->mclk_rate <= 10000000) { - indiv_bits = DA7219_PLL_INDIV_5_10_MHZ; - indiv = DA7219_PLL_INDIV_5_10_MHZ_VAL; - } else if (da7219->mclk_rate <= 20000000) { - indiv_bits = DA7219_PLL_INDIV_10_20_MHZ; - indiv = DA7219_PLL_INDIV_10_20_MHZ_VAL; - } else if (da7219->mclk_rate <= 40000000) { - indiv_bits = DA7219_PLL_INDIV_20_40_MHZ; - indiv = DA7219_PLL_INDIV_20_40_MHZ_VAL; + } else if (da7219->mclk_rate <= 4500000) { + indiv_bits = DA7219_PLL_INDIV_2_TO_4_5_MHZ; + indiv = DA7219_PLL_INDIV_2_TO_4_5_MHZ_VAL; + } else if (da7219->mclk_rate <= 9000000) { + indiv_bits = DA7219_PLL_INDIV_4_5_TO_9_MHZ; + indiv = DA7219_PLL_INDIV_4_5_TO_9_MHZ_VAL; + } else if (da7219->mclk_rate <= 18000000) { + indiv_bits = DA7219_PLL_INDIV_9_TO_18_MHZ; + indiv = DA7219_PLL_INDIV_9_TO_18_MHZ_VAL; + } else if (da7219->mclk_rate <= 36000000) { + indiv_bits = DA7219_PLL_INDIV_18_TO_36_MHZ; + indiv = DA7219_PLL_INDIV_18_TO_36_MHZ_VAL; } else if (da7219->mclk_rate <= 54000000) { - indiv_bits = DA7219_PLL_INDIV_40_54_MHZ; - indiv = DA7219_PLL_INDIV_40_54_MHZ_VAL; + indiv_bits = DA7219_PLL_INDIV_36_TO_54_MHZ; + indiv = DA7219_PLL_INDIV_36_TO_54_MHZ_VAL; } else { dev_err(codec->dev, "PLL input clock %d above valid range\n", da7219->mclk_rate); diff --git a/sound/soc/codecs/da7219.h b/sound/soc/codecs/da7219.h index 5a787e7..ff2a2f0 100644 --- a/sound/soc/codecs/da7219.h +++ b/sound/soc/codecs/da7219.h @@ -194,11 +194,11 @@ /* DA7219_PLL_CTRL = 0x20 */ #define DA7219_PLL_INDIV_SHIFT 2 #define DA7219_PLL_INDIV_MASK (0x7 << 2) -#define DA7219_PLL_INDIV_2_5_MHZ (0x0 << 2) -#define DA7219_PLL_INDIV_5_10_MHZ (0x1 << 2) -#define DA7219_PLL_INDIV_10_20_MHZ (0x2 << 2) -#define DA7219_PLL_INDIV_20_40_MHZ (0x3 << 2) -#define DA7219_PLL_INDIV_40_54_MHZ (0x4 << 2) +#define DA7219_PLL_INDIV_2_TO_4_5_MHZ (0x0 << 2) +#define DA7219_PLL_INDIV_4_5_TO_9_MHZ (0x1 << 2) +#define DA7219_PLL_INDIV_9_TO_18_MHZ (0x2 << 2) +#define DA7219_PLL_INDIV_18_TO_36_MHZ (0x3 << 2) +#define DA7219_PLL_INDIV_36_TO_54_MHZ (0x4 << 2) #define DA7219_PLL_MCLK_SQR_EN_SHIFT 5 #define DA7219_PLL_MCLK_SQR_EN_MASK (0x1 << 5) #define DA7219_PLL_MODE_SHIFT 6 @@ -761,11 +761,11 @@ #define DA7219_PLL_FREQ_OUT_98304 98304000 /* PLL Frequency Dividers */ -#define DA7219_PLL_INDIV_2_5_MHZ_VAL 1 -#define DA7219_PLL_INDIV_5_10_MHZ_VAL 2 -#define DA7219_PLL_INDIV_10_20_MHZ_VAL 4 -#define DA7219_PLL_INDIV_20_40_MHZ_VAL 8 -#define DA7219_PLL_INDIV_40_54_MHZ_VAL 16 +#define DA7219_PLL_INDIV_2_TO_4_5_MHZ_VAL 1 +#define DA7219_PLL_INDIV_4_5_TO_9_MHZ_VAL 2 +#define DA7219_PLL_INDIV_9_TO_18_MHZ_VAL 4 +#define DA7219_PLL_INDIV_18_TO_36_MHZ_VAL 8 +#define DA7219_PLL_INDIV_36_TO_54_MHZ_VAL 16 /* SRM */ #define DA7219_SRM_CHECK_RETRIES 8 -- 1.9.3