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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: 0pAL3jrJKhein5fz6NCbqGjxdfum1dJc X-Proofpoint-ORIG-GUID: 0pAL3jrJKhein5fz6NCbqGjxdfum1dJc X-Authority-Analysis: v=2.4 cv=eaIwvrEH c=1 sm=1 tr=0 ts=68f13b56 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=LqmlnLjRnrQCSl2bsDkM0Q==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Da5OPgB5uXQvAvJx2EkA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDExMDAyMiBTYWx0ZWRfXyws+LAzd+5qP EaxcyxliL8QE1ltyYLiGWhmCe3ZnsvoInymfiedOm0PfmvXsubNHDxG53V02QhMEXpdxPFGu9E6 ywrwXVKeI2wqKwiU1eH2WCdNLoeLMj1A0nEjFaGGH/0Aj3J76+TGkSK07LhlV1XH4GvXLkhZ1K8 DY3PvUwPLzt/xFX/x3POepNuqNQxYwUSxJeZJ8K0A7erPsLEv9jrw9WjOXfMBE8LvNnKrhFzF+g kFCOLqeJaB1XDPyJ/ZiPaiOcLzMYcJDJN2TDt9POGlDts3qhcDOCh/HuIjxUIeqtO6MyttKVEz4 ZKBdQ0i3L7eKxQ3+ZO50LFabrAqcX/vvsh+fhp9ICIXY93S2LtKH3/Kh6ebVkXI7EvYvLJIgs/v 7gQXW0+auuO7VoouY8U55G/bpCRwsA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-16_03,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 spamscore=0 impostorscore=0 phishscore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510110022 On 10/16/2025 7:17 PM, Dmitry Baryshkov wrote: >> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h >> index fe8a39e5e5a3fc68dc3a706ffdba07a5558163cf..6474f561c8dc29d1975bb44792595d86f16b6cff 100644 >> --- a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h >> +++ b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h >> @@ -9,9 +9,38 @@ >> #define VCODEC_BASE_OFFS 0x00000000 >> #define CPU_BASE_OFFS 0x000A0000 >> #define WRAPPER_BASE_OFFS 0x000B0000 >> +#define AON_BASE_OFFS 0x000E0000 >> +#define WRAPPER_TZ_BASE_OFFS 0x000C0000 >> +#define AON_MVP_NOC_RESET 0x0001F000 >> >> #define CPU_CS_BASE_OFFS (CPU_BASE_OFFS) >> >> #define WRAPPER_CORE_POWER_STATUS (WRAPPER_BASE_OFFS + 0x80) >> +#define WRAPPER_CORE_CLOCK_CONFIG (WRAPPER_BASE_OFFS + 0x88) >> +#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS) >> +#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54) >> +#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58) >> +#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C) >> +#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60) >> +#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14) >> +#define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160) >> +#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168) >> +#define AON_WRAPPER_MVP_NOC_RESET_REQ (AON_MVP_NOC_RESET + 0x000) >> +#define AON_WRAPPER_MVP_NOC_RESET_ACK (AON_MVP_NOC_RESET + 0x004) >> +#define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70) >> +#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4) >> +#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18) > Registers here got totally unsorted (they were in the original source > file). Seeing this makes me sad. > Sure, i will be improving this part in v2. >> + >> +#define CORE_BRIDGE_SW_RESET BIT(0) >> +#define CORE_BRIDGE_HW_RESET_DISABLE BIT(1) >> +#define MSK_SIGNAL_FROM_TENSILICA BIT(0) >> +#define MSK_CORE_POWER_ON BIT(1) >> +#define CTL_AXI_CLK_HALT BIT(0) >> +#define CTL_CLK_HALT BIT(1) >> +#define REQ_POWER_DOWN_PREP BIT(0) >> +#define RESET_HIGH BIT(0) >> +#define NOC_LPI_STATUS_DONE BIT(0) /* Indicates the NOC handshake is complete */ >> +#define NOC_LPI_STATUS_DENY BIT(1) /* Indicates the NOC handshake is denied */ >> +#define NOC_LPI_STATUS_ACTIVE BIT(2) /* Indicates the NOC is active */ > Ugh. This mixed all the bits, loosing connection between the register > and the corresponding bits. I'm going to pick up this patch into the > sc7280 series and I will improve it there, keeping the link between > registers and bit fields. > Ok, not updating this part in the next revision of my series. Do you mean something like #define CORE_BRIDGE_SW_RESET_BIT0 BIT(0) #define CORE_BRIDGE_HW_RESET_DISABLE_BIT1 BIT(1) Regards, Vikash