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Thu, 12 Nov 2026 09:36:59 +0100 Message-ID: Date: Thu, 12 Nov 2026 09:36:59 +0100 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/5] dt-bindings: arm: stm32: Add clock-controller sub-node to STM32MP2 SYSCFG To: Conor Dooley CC: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Christophe Roullier , Dario Binacchi , , , , , References: <20261110-ups_mp25_clk_syscfg-v1-0-667829cd290a@foss.st.com> <20261110-ups_mp25_clk_syscfg-v1-2-667829cd290a@foss.st.com> <20261110-confidant-bundle-08385b99bd78@spud> Content-Language: en-US From: Gabriel FERNANDEZ In-Reply-To: <20261110-confidant-bundle-08385b99bd78@spud> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: ENXCAS1NODE2.st.com (10.75.128.138) To STKDAG1NODE2.st.com (10.75.128.133) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DB1PEPF000509E7:EE_|AS8PR10MB7546:EE_ X-MS-Office365-Filtering-Correlation-Id: 157f1756-290f-487a-1953-08df40981ec5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|7416014|376014|82310400026|36860700016|1800799024|4143699003|11063799006|56012099006|261026140227099003|261009223027099003|261022105027099003|261026121527099003|261021121427099003|261028144727099003|261102123227099003|261022075727099003|22082099003|18002099003|10067099003|3023799007; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: p5WFCKE7dc8DUtGymDXbQhDbAyypED6vtFxzoEnU9x8XW5dSQ2/OHGX41LjdLJN32PWxqerfAdMEDoNMxCum5qrGQ1m8cD5Xir1QaqyN69q/+0Yq+GKx68bZGPlSdSiVzBSt5Jp36PmGdijB9S6ikNA8GPhc6LqCmh3/Erf9ratzQgR+q5EqRwkXzThK0Dg9SFPK/1WGlWm/LjxnbYXslixBWzK4PB3Vcx+0tTKDJOJ58cOjCe8n89MVV058vFqVNNHqOZh5IpgBHTG7TR/SE6nVE4otv6NJLCIvkDOlj8vFSViv2Qq7RaxzN6/2OTNoOS4VCooW/sar723Mlj2b4RSz/FbEmsCwmMyUJxz8c/Fy0vi8cr83ikBNnPcnOpeEIUjVvviGLwMAELsNJV1EuTI/VCV7praT5mYHysv88HVfMiCzg/Ar2NZwZ+BALekS X-OriginatorOrg: foss.st.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Nov 2026 08:37:00.4256 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 157f1756-290f-487a-1953-08df40981ec5 X-MS-Exchange-CrossTenant-Id: 75e027c9-20d5-47d5-b82f-77d7cd041e8f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=75e027c9-20d5-47d5-b82f-77d7cd041e8f;Ip=[164.130.1.59];Helo=[smtpO365.st.com] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF000509E7.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR10MB7546 Hi Conor, Thanks for review On 11/10/26 19:54, Conor Dooley wrote: > On Tue, Nov 10, 2026 at 11:42:17AM +0100, Gabriel Fernandez wrote: >> The LTDC pixel clock multiplexer of the STM32MP23x and STM32MP25x >> SYSCFG is described by a clock-controller sub-node of the SYSCFG node. >> >> Add this sub-node to the SYSCFG binding. It is required on STM32MP23x >> and STM32MP25x and not allowed on the other SoCs. >> >> Signed-off-by: Gabriel Fernandez > Why does this need a child node at all, can't the clock controller > properties go straight into this syscon node? > > Cheers, > Conor. I sent a v2 [1] shortly before your reply, which explains this in the commit message, but the question still applies to it, so let me answer here. From a hardware point of view, the mux inputs could indeed be described in the SYSCFG node. The problem is that this node is a "syscon": when the syscon core creates the regmap of the node (syscon_node_to_regmap() or syscon_regmap_lookup_by_*()), it takes the first clock of the node as the clock of the registers, keeps it prepared and enables/disables it around each register access. The SYSCFG has no clock gate in the RCC, so this first clock would be the LTDC kernel clock, i.e. the first input of the mux. It would then be enabled on every SYSCFG access by all the users of this syscon (PCIe, ComboPHY, Ethernet, OMM...). Registering our own regmap with of_syscon_register_regmap() from the SYSCFG driver doesn't solve it either: these users reach the SYSCFG through vendor phandles (st,syscon, st,syscfg-amcr) or by compatible, which are not tracked by fw_devlink, so one of them can create the syscon regmap, with the clock, before the SYSCFG driver probes. Apart from adding a dummy clock in first position, which would describe something which doesn't exist in the hardware, I didn't find a way to keep these properties in the SYSCFG node. So the mux is described by a sub-node with its own clock inputs, like the USB2 PHYs of the SYSCFG which are already described as sub-nodes. In v2, the '#clock-cells' property of the SYSCFG node is deprecated, so that the sub-node is the only provider of this clock. No driver ever registered a clock on the SYSCFG node, so this doesn't change anything for existing devicetrees. [1] https://lore.kernel.org/r/20261110-ups_mp25_clk_syscfg-v2-0-624559bb8ec7@foss.st.com Best regards, Gabriel > >> --- >> Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml | 6 ++++++ >> 1 file changed, 6 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml >> index a559f8b03b84..38c844e8f19d 100644 >> --- a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml >> +++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml >> @@ -45,6 +45,10 @@ properties: >> "#size-cells": >> const: 1 >> >> + clock-controller: >> + type: object >> + $ref: /schemas/clock/st,stm32mp25-syscfg-clk.yaml# >> + >> patternProperties: >> "^phy@2[48]00$": >> type: object >> @@ -80,6 +84,7 @@ allOf: >> - "#address-cells" >> - "#clock-cells" >> - "#size-cells" >> + - clock-controller >> - phy@2400 >> - phy@2800 >> else: >> @@ -87,6 +92,7 @@ allOf: >> '#address-cells': false >> '#clock-cells': false >> '#size-cells': false >> + clock-controller: false >> phy@2400: false >> phy@2800: false >> >> >> -- >> 2.43.0 >>