From: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
To: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>,
Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>,
Abhinav Kumar <abhinav.kumar@linux.dev>,
Bryan O'Donoghue <bod@kernel.org>,
Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v7 8/8] media: qcom: iris: split platform data from firmware data
Date: Wed, 18 Mar 2026 15:56:33 +0530 [thread overview]
Message-ID: <c510b9a4-2ed5-4b55-b294-44f4c7983379@oss.qualcomm.com> (raw)
In-Reply-To: <20260316-iris-platform-data-v7-8-fc79f003f51c@oss.qualcomm.com>
On 3/17/2026 12:24 AM, Dmitry Baryshkov wrote:
> Finalize the logical separation of the software and hardware interface
> descriptions by moving hardware properties to the files specific to the
> particular VPU version.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/media/platform/qcom/iris/Makefile | 6 +-
> .../iris/{iris_platform_gen1.c => iris_hfi_gen1.c} | 136 -------------
> .../iris/{iris_platform_gen2.c => iris_hfi_gen2.c} | 223 ---------------------
> .../platform/qcom/iris/iris_platform_common.h | 3 +
> .../platform/qcom/iris/iris_platform_sm8250.h | 29 +++
> .../platform/qcom/iris/iris_platform_sm8550.h | 31 +++
> .../media/platform/qcom/iris/iris_platform_vpu2.c | 126 ++++++++++++
> .../media/platform/qcom/iris/iris_platform_vpu3x.c | 214 ++++++++++++++++++++
> 8 files changed, 407 insertions(+), 361 deletions(-)
>
> diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/platform/qcom/iris/Makefile
> index 2fde45f81727..48e415cbc439 100644
> --- a/drivers/media/platform/qcom/iris/Makefile
> +++ b/drivers/media/platform/qcom/iris/Makefile
> @@ -4,14 +4,16 @@ qcom-iris-objs += iris_buffer.o \
> iris_ctrls.o \
> iris_firmware.o \
> iris_hfi_common.o \
> + iris_hfi_gen1.o \
> iris_hfi_gen1_command.o \
> iris_hfi_gen1_response.o \
> + iris_hfi_gen2.o \
> iris_hfi_gen2_command.o \
> iris_hfi_gen2_packet.o \
> iris_hfi_gen2_response.o \
> iris_hfi_queue.o \
> - iris_platform_gen1.o \
> - iris_platform_gen2.o \
> + iris_platform_vpu2.o \
> + iris_platform_vpu3x.o \
> iris_power.o \
> iris_probe.o \
> iris_resources.o \
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/drivers/media/platform/qcom/iris/iris_hfi_gen1.c
> similarity index 67%
> rename from drivers/media/platform/qcom/iris/iris_platform_gen1.c
> rename to drivers/media/platform/qcom/iris/iris_hfi_gen1.c
> index b2d18459a811..60f51a1ba941 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c
> +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1.c
> @@ -3,38 +3,16 @@
> * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
> */
>
> -#include "iris_core.h"
> #include "iris_ctrls.h"
> #include "iris_platform_common.h"
> -#include "iris_resources.h"
> #include "iris_hfi_gen1.h"
> #include "iris_hfi_gen1_defines.h"
> #include "iris_vpu_buffer.h"
> -#include "iris_vpu_common.h"
> -#include "iris_instance.h"
> -
> -#include "iris_platform_sc7280.h"
>
> #define BITRATE_MIN 32000
> #define BITRATE_MAX 160000000
> -#define BITRATE_PEAK_DEFAULT (BITRATE_DEFAULT * 2)
> #define BITRATE_STEP 100
>
> -static struct iris_fmt platform_fmts_sm8250_dec[] = {
> - [IRIS_FMT_H264] = {
> - .pixfmt = V4L2_PIX_FMT_H264,
> - .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
> - },
> - [IRIS_FMT_HEVC] = {
> - .pixfmt = V4L2_PIX_FMT_HEVC,
> - .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
> - },
> - [IRIS_FMT_VP9] = {
> - .pixfmt = V4L2_PIX_FMT_VP9,
> - .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
> - },
> -};
> -
> static struct platform_inst_fw_cap inst_fw_cap_sm8250_dec[] = {
> {
> .cap_id = PIPE,
> @@ -248,56 +226,6 @@ static const struct platform_inst_fw_cap inst_fw_cap_sm8250_enc[] = {
> },
> };
>
> -static struct platform_inst_caps platform_inst_cap_sm8250 = {
> - .min_frame_width = 128,
> - .max_frame_width = 8192,
> - .min_frame_height = 128,
> - .max_frame_height = 8192,
> - .max_mbpf = 138240,
> - .mb_cycles_vsp = 25,
> - .mb_cycles_vpp = 200,
> - .max_frame_rate = MAXIMUM_FPS,
> - .max_operating_rate = MAXIMUM_FPS,
> -};
> -
> -static const struct icc_info sm8250_icc_table[] = {
> - { "cpu-cfg", 1000, 1000 },
> - { "video-mem", 1000, 15000000 },
> -};
> -
> -static const char * const sm8250_clk_reset_table[] = { "bus", "core" };
> -
> -static const struct bw_info sm8250_bw_table_dec[] = {
> - { ((4096 * 2160) / 256) * 60, 2403000 },
> - { ((4096 * 2160) / 256) * 30, 1224000 },
> - { ((1920 * 1080) / 256) * 60, 812000 },
> - { ((1920 * 1080) / 256) * 30, 416000 },
> -};
> -
> -static const char * const sm8250_pmdomain_table[] = { "venus", "vcodec0" };
> -
> -static const char * const sm8250_opp_pd_table[] = { "mx", "mmcx" };
> -
> -static const struct platform_clk_data sm8250_clk_table[] = {
> - {IRIS_AXI_CLK, "iface" },
> - {IRIS_CTRL_CLK, "core" },
> - {IRIS_HW_CLK, "vcodec0_core" },
> -};
> -
> -static const char * const sm8250_opp_clk_table[] = {
> - "vcodec0_core",
> - NULL,
> -};
> -
> -static const struct tz_cp_config tz_cp_config_sm8250[] = {
> - {
> - .cp_start = 0,
> - .cp_size = 0x25800000,
> - .cp_nonpixel_start = 0x01000000,
> - .cp_nonpixel_size = 0x24800000,
> - },
> -};
> -
> static const u32 sm8250_vdec_input_config_param_default[] = {
> HFI_PROPERTY_CONFIG_VIDEOCORES_USAGE,
> HFI_PROPERTY_PARAM_UNCOMPRESSED_FORMAT_SELECT,
> @@ -356,67 +284,3 @@ const struct iris_firmware_data iris_hfi_gen1_data = {
> .enc_ip_int_buf_tbl = sm8250_enc_ip_int_buf_tbl,
> .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl),
> };
> -
> -const struct iris_platform_data sm8250_data = {
> - .firmware_data = &iris_hfi_gen1_data,
> - .get_vpu_buffer_size = iris_vpu_buf_size,
> - .vpu_ops = &iris_vpu2_ops,
> - .icc_tbl = sm8250_icc_table,
> - .icc_tbl_size = ARRAY_SIZE(sm8250_icc_table),
> - .clk_rst_tbl = sm8250_clk_reset_table,
> - .clk_rst_tbl_size = ARRAY_SIZE(sm8250_clk_reset_table),
> - .bw_tbl_dec = sm8250_bw_table_dec,
> - .bw_tbl_dec_size = ARRAY_SIZE(sm8250_bw_table_dec),
> - .pmdomain_tbl = sm8250_pmdomain_table,
> - .pmdomain_tbl_size = ARRAY_SIZE(sm8250_pmdomain_table),
> - .opp_pd_tbl = sm8250_opp_pd_table,
> - .opp_pd_tbl_size = ARRAY_SIZE(sm8250_opp_pd_table),
> - .clk_tbl = sm8250_clk_table,
> - .clk_tbl_size = ARRAY_SIZE(sm8250_clk_table),
> - .opp_clk_tbl = sm8250_opp_clk_table,
> - /* Upper bound of DMA address range */
> - .dma_mask = 0xe0000000 - 1,
> - .fwname = "qcom/vpu-1.0/venus.mbn",
> - .inst_iris_fmts = platform_fmts_sm8250_dec,
> - .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8250_dec),
> - .inst_caps = &platform_inst_cap_sm8250,
> - .tz_cp_config_data = tz_cp_config_sm8250,
> - .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8250),
> - .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
This can be moved out and is not bound to any specific platform.
> - .num_vpp_pipe = 4,
> - .max_session_count = 16,
> - .max_core_mbpf = NUM_MBS_8K,
> - .max_core_mbps = ((7680 * 4320) / 256) * 60,
> -};
> -
> -const struct iris_platform_data sc7280_data = {
> - .firmware_data = &iris_hfi_gen1_data,
> - .get_vpu_buffer_size = iris_vpu_buf_size,
> - .vpu_ops = &iris_vpu2_ops,
> - .icc_tbl = sm8250_icc_table,
> - .icc_tbl_size = ARRAY_SIZE(sm8250_icc_table),
> - .bw_tbl_dec = sc7280_bw_table_dec,
> - .bw_tbl_dec_size = ARRAY_SIZE(sc7280_bw_table_dec),
> - .pmdomain_tbl = sm8250_pmdomain_table,
> - .pmdomain_tbl_size = ARRAY_SIZE(sm8250_pmdomain_table),
> - .opp_pd_tbl = sc7280_opp_pd_table,
> - .opp_pd_tbl_size = ARRAY_SIZE(sc7280_opp_pd_table),
> - .clk_tbl = sc7280_clk_table,
> - .clk_tbl_size = ARRAY_SIZE(sc7280_clk_table),
> - .opp_clk_tbl = sc7280_opp_clk_table,
> - /* Upper bound of DMA address range */
> - .dma_mask = 0xe0000000 - 1,
> - .fwname = "qcom/vpu/vpu20_p1.mbn",
> - .inst_iris_fmts = platform_fmts_sm8250_dec,
> - .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8250_dec),
> - .inst_caps = &platform_inst_cap_sm8250,
> - .tz_cp_config_data = tz_cp_config_sm8250,
> - .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8250),
> - .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
> - .num_vpp_pipe = 1,
> - .no_aon = true,
> - .max_session_count = 16,
> - .max_core_mbpf = 4096 * 2176 / 256 * 2 + 1920 * 1088 / 256,
> - /* max spec for SC7280 is 4096x2176@60fps */
> - .max_core_mbps = 4096 * 2176 / 256 * 60,
> -};
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_hfi_gen2.c
> similarity index 76%
> rename from drivers/media/platform/qcom/iris/iris_platform_gen2.c
> rename to drivers/media/platform/qcom/iris/iris_hfi_gen2.c
> index 1a54a9a96285..071009a9ce4c 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2.c
> @@ -4,40 +4,14 @@
> * Copyright (c) 2025 Linaro Ltd
> */
>
> -#include "iris_core.h"
> #include "iris_ctrls.h"
> #include "iris_hfi_gen2.h"
> #include "iris_hfi_gen2_defines.h"
> #include "iris_platform_common.h"
> #include "iris_vpu_buffer.h"
> -#include "iris_vpu_common.h"
>
> -#include "iris_platform_qcs8300.h"
> -#include "iris_platform_sm8650.h"
> -#include "iris_platform_sm8750.h"
> -
> -#define VIDEO_ARCH_LX 1
> #define BITRATE_MAX 245000000
>
> -static struct iris_fmt platform_fmts_sm8550_dec[] = {
> - [IRIS_FMT_H264] = {
> - .pixfmt = V4L2_PIX_FMT_H264,
> - .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
> - },
> - [IRIS_FMT_HEVC] = {
> - .pixfmt = V4L2_PIX_FMT_HEVC,
> - .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
> - },
> - [IRIS_FMT_VP9] = {
> - .pixfmt = V4L2_PIX_FMT_VP9,
> - .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
> - },
> - [IRIS_FMT_AV1] = {
> - .pixfmt = V4L2_PIX_FMT_AV1,
> - .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
> - },
> -};
> -
> static const struct platform_inst_fw_cap inst_fw_cap_sm8550_dec[] = {
> {
> .cap_id = PROFILE_H264,
> @@ -742,58 +716,6 @@ static const struct platform_inst_fw_cap inst_fw_cap_sm8550_enc[] = {
> },
> };
>
> -static struct platform_inst_caps platform_inst_cap_sm8550 = {
> - .min_frame_width = 96,
> - .max_frame_width = 8192,
> - .min_frame_height = 96,
> - .max_frame_height = 8192,
> - .max_mbpf = (8192 * 4352) / 256,
> - .mb_cycles_vpp = 200,
> - .mb_cycles_fw = 489583,
> - .mb_cycles_fw_vpp = 66234,
> - .num_comv = 0,
> - .max_frame_rate = MAXIMUM_FPS,
> - .max_operating_rate = MAXIMUM_FPS,
> -};
> -
> -static const struct icc_info sm8550_icc_table[] = {
> - { "cpu-cfg", 1000, 1000 },
> - { "video-mem", 1000, 15000000 },
> -};
> -
> -static const char * const sm8550_clk_reset_table[] = { "bus" };
> -
> -static const struct bw_info sm8550_bw_table_dec[] = {
> - { ((4096 * 2160) / 256) * 60, 1608000 },
> - { ((4096 * 2160) / 256) * 30, 826000 },
> - { ((1920 * 1080) / 256) * 60, 567000 },
> - { ((1920 * 1080) / 256) * 30, 294000 },
> -};
> -
> -static const char * const sm8550_pmdomain_table[] = { "venus", "vcodec0" };
> -
> -static const char * const sm8550_opp_pd_table[] = { "mxc", "mmcx" };
> -
> -static const struct platform_clk_data sm8550_clk_table[] = {
> - {IRIS_AXI_CLK, "iface" },
> - {IRIS_CTRL_CLK, "core" },
> - {IRIS_HW_CLK, "vcodec0_core" },
> -};
> -
> -static const char * const sm8550_opp_clk_table[] = {
> - "vcodec0_core",
> - NULL,
> -};
> -
> -static const struct tz_cp_config tz_cp_config_sm8550[] = {
> - {
> - .cp_start = 0,
> - .cp_size = 0x25800000,
> - .cp_nonpixel_start = 0x01000000,
> - .cp_nonpixel_size = 0x24800000,
> - },
> -};
> -
> static const u32 sm8550_vdec_input_config_params_default[] = {
> HFI_PROP_BITSTREAM_RESOLUTION,
> HFI_PROP_CROP_OFFSETS,
> @@ -969,148 +891,3 @@ const struct iris_firmware_data iris_hfi_gen2_data = {
> .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl,
> .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
> };
> -
> -const struct iris_platform_data sm8550_data = {
> - .firmware_data = &iris_hfi_gen2_data,
> - .get_vpu_buffer_size = iris_vpu_buf_size,
> - .vpu_ops = &iris_vpu3_ops,
> - .icc_tbl = sm8550_icc_table,
> - .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table),
> - .clk_rst_tbl = sm8550_clk_reset_table,
> - .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table),
> - .bw_tbl_dec = sm8550_bw_table_dec,
> - .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec),
> - .pmdomain_tbl = sm8550_pmdomain_table,
> - .pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table),
> - .opp_pd_tbl = sm8550_opp_pd_table,
> - .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
> - .clk_tbl = sm8550_clk_table,
> - .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
> - .opp_clk_tbl = sm8550_opp_clk_table,
> - /* Upper bound of DMA address range */
> - .dma_mask = 0xe0000000 - 1,
> - .fwname = "qcom/vpu/vpu30_p4.mbn",
> - .inst_iris_fmts = platform_fmts_sm8550_dec,
> - .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec),
> - .inst_caps = &platform_inst_cap_sm8550,
> - .tz_cp_config_data = tz_cp_config_sm8550,
> - .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550),
> - .core_arch = VIDEO_ARCH_LX,
> - .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
> - .num_vpp_pipe = 4,
> - .max_session_count = 16,
> - .max_core_mbpf = NUM_MBS_8K * 2,
> - .max_core_mbps = ((7680 * 4320) / 256) * 60,
> -};
> -
> -/*
> - * Shares most of SM8550 data except:
> - * - vpu_ops to iris_vpu33_ops
> - * - clk_rst_tbl to sm8650_clk_reset_table
> - * - controller_rst_tbl to sm8650_controller_reset_table
> - * - fwname to "qcom/vpu/vpu33_p4.mbn"
> - */
> -const struct iris_platform_data sm8650_data = {
> - .firmware_data = &iris_hfi_gen2_data,
> - .get_vpu_buffer_size = iris_vpu33_buf_size,
> - .vpu_ops = &iris_vpu33_ops,
> - .icc_tbl = sm8550_icc_table,
> - .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table),
> - .clk_rst_tbl = sm8650_clk_reset_table,
> - .clk_rst_tbl_size = ARRAY_SIZE(sm8650_clk_reset_table),
> - .controller_rst_tbl = sm8650_controller_reset_table,
> - .controller_rst_tbl_size = ARRAY_SIZE(sm8650_controller_reset_table),
> - .bw_tbl_dec = sm8550_bw_table_dec,
> - .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec),
> - .pmdomain_tbl = sm8550_pmdomain_table,
> - .pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table),
> - .opp_pd_tbl = sm8550_opp_pd_table,
> - .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
> - .clk_tbl = sm8550_clk_table,
> - .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
> - .opp_clk_tbl = sm8550_opp_clk_table,
> - /* Upper bound of DMA address range */
> - .dma_mask = 0xe0000000 - 1,
> - .fwname = "qcom/vpu/vpu33_p4.mbn",
> - .inst_iris_fmts = platform_fmts_sm8550_dec,
> - .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec),
> - .inst_caps = &platform_inst_cap_sm8550,
> - .tz_cp_config_data = tz_cp_config_sm8550,
> - .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550),
> - .core_arch = VIDEO_ARCH_LX,
> - .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
> - .num_vpp_pipe = 4,
> - .max_session_count = 16,
> - .max_core_mbpf = NUM_MBS_8K * 2,
> - .max_core_mbps = ((7680 * 4320) / 256) * 60,
> -};
> -
> -const struct iris_platform_data sm8750_data = {
> - .firmware_data = &iris_hfi_gen2_data,
> - .get_vpu_buffer_size = iris_vpu33_buf_size,
> - .vpu_ops = &iris_vpu35_ops,
> - .icc_tbl = sm8550_icc_table,
> - .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table),
> - .clk_rst_tbl = sm8750_clk_reset_table,
> - .clk_rst_tbl_size = ARRAY_SIZE(sm8750_clk_reset_table),
> - .bw_tbl_dec = sm8550_bw_table_dec,
> - .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec),
> - .pmdomain_tbl = sm8550_pmdomain_table,
> - .pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table),
> - .opp_pd_tbl = sm8550_opp_pd_table,
> - .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
> - .clk_tbl = sm8750_clk_table,
> - .clk_tbl_size = ARRAY_SIZE(sm8750_clk_table),
> - .opp_clk_tbl = sm8550_opp_clk_table,
> - /* Upper bound of DMA address range */
> - .dma_mask = 0xe0000000 - 1,
> - .fwname = "qcom/vpu/vpu35_p4.mbn",
> - .inst_iris_fmts = platform_fmts_sm8550_dec,
> - .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec),
> - .inst_caps = &platform_inst_cap_sm8550,
> - .tz_cp_config_data = tz_cp_config_sm8550,
> - .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550),
> - .core_arch = VIDEO_ARCH_LX,
> - .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
> - .num_vpp_pipe = 4,
> - .max_session_count = 16,
> - .max_core_mbpf = NUM_MBS_8K * 2,
> - .max_core_mbps = ((7680 * 4320) / 256) * 60,
> -};
> -
> -/*
> - * Shares most of SM8550 data except:
> - * - inst_caps to platform_inst_cap_qcs8300
> - */
> -const struct iris_platform_data qcs8300_data = {
> - .firmware_data = &iris_hfi_gen2_data,
> - .get_vpu_buffer_size = iris_vpu_buf_size,
> - .vpu_ops = &iris_vpu3_ops,
> - .icc_tbl = sm8550_icc_table,
> - .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table),
> - .clk_rst_tbl = sm8550_clk_reset_table,
> - .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table),
> - .bw_tbl_dec = sm8550_bw_table_dec,
> - .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec),
> - .pmdomain_tbl = sm8550_pmdomain_table,
> - .pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table),
> - .opp_pd_tbl = sm8550_opp_pd_table,
> - .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
> - .clk_tbl = sm8550_clk_table,
> - .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
> - .opp_clk_tbl = sm8550_opp_clk_table,
> - /* Upper bound of DMA address range */
> - .dma_mask = 0xe0000000 - 1,
> - .fwname = "qcom/vpu/vpu30_p4_s6.mbn",
> - .inst_iris_fmts = platform_fmts_sm8550_dec,
> - .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec),
> - .inst_caps = &platform_inst_cap_qcs8300,
> - .tz_cp_config_data = tz_cp_config_sm8550,
> - .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550),
> - .core_arch = VIDEO_ARCH_LX,
> - .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
> - .num_vpp_pipe = 2,
> - .max_session_count = 16,
> - .max_core_mbpf = ((4096 * 2176) / 256) * 4,
> - .max_core_mbps = (((3840 * 2176) / 256) * 120),
> -};
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
> index 401069bd7396..39a7ee8ce904 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_common.h
> +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
> @@ -40,6 +40,9 @@ enum pipe_type {
> PIPE_4 = 4,
> };
>
> +extern const struct iris_firmware_data iris_hfi_gen1_data;
> +extern const struct iris_firmware_data iris_hfi_gen2_data;
> +
> extern const struct iris_platform_data qcs8300_data;
> extern const struct iris_platform_data sc7280_data;
> extern const struct iris_platform_data sm8250_data;
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.h b/drivers/media/platform/qcom/iris/iris_platform_sm8250.h
> new file mode 100644
> index 000000000000..50306043eb8e
> --- /dev/null
> +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.h
> @@ -0,0 +1,29 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +#ifndef __IRIS_PLATFORM_SM8250_H__
> +#define __IRIS_PLATFORM_SM8250_H__
> +
> +static const struct bw_info sm8250_bw_table_dec[] = {
> + { ((4096 * 2160) / 256) * 60, 2403000 },
> + { ((4096 * 2160) / 256) * 30, 1224000 },
> + { ((1920 * 1080) / 256) * 60, 812000 },
> + { ((1920 * 1080) / 256) * 30, 416000 },
> +};
> +
> +static const char * const sm8250_opp_pd_table[] = { "mx", "mmcx" };
> +
> +static const struct platform_clk_data sm8250_clk_table[] = {
> + {IRIS_AXI_CLK, "iface" },
> + {IRIS_CTRL_CLK, "core" },
> + {IRIS_HW_CLK, "vcodec0_core" },
> +};
> +
> +static const char * const sm8250_opp_clk_table[] = {
> + "vcodec0_core",
> + NULL,
> +};
> +
> +#endif
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8550.h b/drivers/media/platform/qcom/iris/iris_platform_sm8550.h
> new file mode 100644
> index 000000000000..a9d9709c2e35
> --- /dev/null
> +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8550.h
> @@ -0,0 +1,31 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#ifndef __IRIS_PLATFORM_SM8550_H__
> +#define __IRIS_PLATFORM_SM8550_H__
> +
> +static const char * const sm8550_clk_reset_table[] = { "bus" };
> +
> +static const struct platform_clk_data sm8550_clk_table[] = {
> + {IRIS_AXI_CLK, "iface" },
> + {IRIS_CTRL_CLK, "core" },
> + {IRIS_HW_CLK, "vcodec0_core" },
> +};
> +
> +static struct platform_inst_caps platform_inst_cap_sm8550 = {
> + .min_frame_width = 96,
> + .max_frame_width = 8192,
> + .min_frame_height = 96,
> + .max_frame_height = 8192,
> + .max_mbpf = (8192 * 4352) / 256,
> + .mb_cycles_vpp = 200,
> + .mb_cycles_fw = 489583,
> + .mb_cycles_fw_vpp = 66234,
> + .num_comv = 0,
> + .max_frame_rate = MAXIMUM_FPS,
> + .max_operating_rate = MAXIMUM_FPS,
> +};
> +
> +#endif
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c
> new file mode 100644
> index 000000000000..b3f5fddd43c2
> --- /dev/null
> +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c
> @@ -0,0 +1,126 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include "iris_core.h"
> +#include "iris_ctrls.h"
> +#include "iris_platform_common.h"
> +#include "iris_resources.h"
> +#include "iris_hfi_gen1.h"
> +#include "iris_hfi_gen1_defines.h"
> +#include "iris_vpu_buffer.h"
> +#include "iris_vpu_common.h"
> +#include "iris_instance.h"
> +
> +#include "iris_platform_sc7280.h"
> +#include "iris_platform_sm8250.h"
> +
> +static struct iris_fmt iris_fmts_vpu2_dec[] = {
> + [IRIS_FMT_H264] = {
> + .pixfmt = V4L2_PIX_FMT_H264,
> + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
> + },
> + [IRIS_FMT_HEVC] = {
> + .pixfmt = V4L2_PIX_FMT_HEVC,
> + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
> + },
> + [IRIS_FMT_VP9] = {
> + .pixfmt = V4L2_PIX_FMT_VP9,
> + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
> + },
> +};
> +
> +static struct platform_inst_caps platform_inst_cap_vpu2 = {
> + .min_frame_width = 128,
> + .max_frame_width = 8192,
> + .min_frame_height = 128,
> + .max_frame_height = 8192,
> + .max_mbpf = 138240,
> + .mb_cycles_vsp = 25,
> + .mb_cycles_vpp = 200,
> + .max_frame_rate = MAXIMUM_FPS,
> + .max_operating_rate = MAXIMUM_FPS,
> +};
> +
> +static const struct icc_info iris_icc_info_vpu2[] = {
> + { "cpu-cfg", 1000, 1000 },
> + { "video-mem", 1000, 15000000 },
> +};
> +
> +static const char * const iris_clk_reset_table_vpu2[] = { "bus", "core" };
> +
> +static const char * const iris_pmdomain_table_vpu2[] = { "venus", "vcodec0" };
> +
> +static const struct tz_cp_config tz_cp_config_vpu2[] = {
> + {
> + .cp_start = 0,
> + .cp_size = 0x25800000,
> + .cp_nonpixel_start = 0x01000000,
> + .cp_nonpixel_size = 0x24800000,
> + },
> +};
> +
> +const struct iris_platform_data sc7280_data = {
> + .firmware_data = &iris_hfi_gen1_data,
> + .get_vpu_buffer_size = iris_vpu_buf_size,
> + .vpu_ops = &iris_vpu2_ops,
> + .icc_tbl = iris_icc_info_vpu2,
> + .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu2),
> + .bw_tbl_dec = sc7280_bw_table_dec,
> + .bw_tbl_dec_size = ARRAY_SIZE(sc7280_bw_table_dec),
> + .pmdomain_tbl = iris_pmdomain_table_vpu2,
> + .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu2),
> + .opp_pd_tbl = sc7280_opp_pd_table,
> + .opp_pd_tbl_size = ARRAY_SIZE(sc7280_opp_pd_table),
> + .clk_tbl = sc7280_clk_table,
> + .clk_tbl_size = ARRAY_SIZE(sc7280_clk_table),
> + .opp_clk_tbl = sc7280_opp_clk_table,
> + /* Upper bound of DMA address range */
> + .dma_mask = 0xe0000000 - 1,
> + .fwname = "qcom/vpu/vpu20_p1.mbn",
> + .inst_iris_fmts = iris_fmts_vpu2_dec,
> + .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu2_dec),
> + .inst_caps = &platform_inst_cap_vpu2,
> + .tz_cp_config_data = tz_cp_config_vpu2,
> + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu2),
> + .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
> + .num_vpp_pipe = 1,
> + .no_aon = true,
> + .max_session_count = 16,
> + .max_core_mbpf = 4096 * 2176 / 256 * 2 + 1920 * 1088 / 256,
> + /* max spec for SC7280 is 4096x2176@60fps */
> + .max_core_mbps = 4096 * 2176 / 256 * 60,
> +};
> +
> +const struct iris_platform_data sm8250_data = {
> + .firmware_data = &iris_hfi_gen1_data,
> + .get_vpu_buffer_size = iris_vpu_buf_size,
> + .vpu_ops = &iris_vpu2_ops,
> + .icc_tbl = iris_icc_info_vpu2,
> + .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu2),
> + .clk_rst_tbl = iris_clk_reset_table_vpu2,
> + .clk_rst_tbl_size = ARRAY_SIZE(iris_clk_reset_table_vpu2),
> + .bw_tbl_dec = sm8250_bw_table_dec,
> + .bw_tbl_dec_size = ARRAY_SIZE(sm8250_bw_table_dec),
> + .pmdomain_tbl = iris_pmdomain_table_vpu2,
> + .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu2),
> + .opp_pd_tbl = sm8250_opp_pd_table,
> + .opp_pd_tbl_size = ARRAY_SIZE(sm8250_opp_pd_table),
> + .clk_tbl = sm8250_clk_table,
> + .clk_tbl_size = ARRAY_SIZE(sm8250_clk_table),
> + .opp_clk_tbl = sm8250_opp_clk_table,
> + /* Upper bound of DMA address range */
> + .dma_mask = 0xe0000000 - 1,
> + .fwname = "qcom/vpu-1.0/venus.mbn",
> + .inst_iris_fmts = iris_fmts_vpu2_dec,
> + .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu2_dec),
> + .inst_caps = &platform_inst_cap_vpu2,
> + .tz_cp_config_data = tz_cp_config_vpu2,
> + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu2),
> + .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
> + .num_vpp_pipe = 4,
> + .max_session_count = 16,
> + .max_core_mbpf = NUM_MBS_8K,
> + .max_core_mbps = ((7680 * 4320) / 256) * 60,
> +};
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c
> new file mode 100644
> index 000000000000..11ca098ab125
> --- /dev/null
> +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c
> @@ -0,0 +1,214 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved.
> + * Copyright (c) 2025 Linaro Ltd
> + */
> +
> +#include "iris_core.h"
> +#include "iris_ctrls.h"
> +#include "iris_hfi_gen2.h"
> +#include "iris_hfi_gen2_defines.h"
> +#include "iris_platform_common.h"
> +#include "iris_vpu_buffer.h"
> +#include "iris_vpu_common.h"
> +
> +#include "iris_platform_qcs8300.h"
> +#include "iris_platform_sm8550.h"
> +#include "iris_platform_sm8650.h"
> +#include "iris_platform_sm8750.h"
> +
> +#define VIDEO_ARCH_LX 1
> +
> +static struct iris_fmt iris_fmts_vpu3x_dec[] = {
> + [IRIS_FMT_H264] = {
> + .pixfmt = V4L2_PIX_FMT_H264,
> + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
> + },
> + [IRIS_FMT_HEVC] = {
> + .pixfmt = V4L2_PIX_FMT_HEVC,
> + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
> + },
> + [IRIS_FMT_VP9] = {
> + .pixfmt = V4L2_PIX_FMT_VP9,
> + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
> + },
> + [IRIS_FMT_AV1] = {
> + .pixfmt = V4L2_PIX_FMT_AV1,
> + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
> + },
> +};
> +
> +static const struct icc_info iris_icc_info_vpu3x[] = {
> + { "cpu-cfg", 1000, 1000 },
> + { "video-mem", 1000, 15000000 },
> +};
> +
> +static const struct bw_info iris_bw_table_dec_vpu3x[] = {
> + { ((4096 * 2160) / 256) * 60, 1608000 },
> + { ((4096 * 2160) / 256) * 30, 826000 },
> + { ((1920 * 1080) / 256) * 60, 567000 },
> + { ((1920 * 1080) / 256) * 30, 294000 },
> +};
> +
> +static const char * const iris_pmdomain_table_vpu3x[] = { "venus", "vcodec0" };
> +
> +static const char * const iris_opp_pd_table_vpu3x[] = { "mxc", "mmcx" };
> +
> +static const char * const iris_opp_clk_table_vpu3x[] = {
> + "vcodec0_core",
> + NULL,
> +};
> +
> +static const struct tz_cp_config tz_cp_config_vpu3[] = {
> + {
> + .cp_start = 0,
> + .cp_size = 0x25800000,
> + .cp_nonpixel_start = 0x01000000,
> + .cp_nonpixel_size = 0x24800000,
> + },
> +};
> +
> +/*
> + * Shares most of SM8550 data except:
> + * - inst_caps to platform_inst_cap_qcs8300
> + */
> +const struct iris_platform_data qcs8300_data = {
> + .firmware_data = &iris_hfi_gen2_data,
> + .get_vpu_buffer_size = iris_vpu_buf_size,
> + .vpu_ops = &iris_vpu3_ops,
> + .icc_tbl = iris_icc_info_vpu3x,
> + .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x),
> + .clk_rst_tbl = sm8550_clk_reset_table,
> + .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table),
> + .bw_tbl_dec = iris_bw_table_dec_vpu3x,
> + .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x),
> + .pmdomain_tbl = iris_pmdomain_table_vpu3x,
> + .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu3x),
> + .opp_pd_tbl = iris_opp_pd_table_vpu3x,
> + .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x),
> + .clk_tbl = sm8550_clk_table,
> + .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
> + .opp_clk_tbl = iris_opp_clk_table_vpu3x,
> + /* Upper bound of DMA address range */
> + .dma_mask = 0xe0000000 - 1,
> + .fwname = "qcom/vpu/vpu30_p4_s6.mbn",
> + .inst_iris_fmts = iris_fmts_vpu3x_dec,
> + .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec),
> + .inst_caps = &platform_inst_cap_qcs8300,
> + .tz_cp_config_data = tz_cp_config_vpu3,
> + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3),
> + .core_arch = VIDEO_ARCH_LX,
> + .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
> + .num_vpp_pipe = 2,
> + .max_session_count = 16,
> + .max_core_mbpf = ((4096 * 2176) / 256) * 4,
> + .max_core_mbps = (((3840 * 2176) / 256) * 120),
> +};
> +
> +const struct iris_platform_data sm8550_data = {
> + .firmware_data = &iris_hfi_gen2_data,
> + .get_vpu_buffer_size = iris_vpu_buf_size,
> + .vpu_ops = &iris_vpu3_ops,
> + .icc_tbl = iris_icc_info_vpu3x,
> + .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x),
> + .clk_rst_tbl = sm8550_clk_reset_table,
> + .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table),
> + .bw_tbl_dec = iris_bw_table_dec_vpu3x,
> + .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x),
> + .pmdomain_tbl = iris_pmdomain_table_vpu3x,
> + .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu3x),
> + .opp_pd_tbl = iris_opp_pd_table_vpu3x,
> + .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x),
> + .clk_tbl = sm8550_clk_table,
> + .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
> + .opp_clk_tbl = iris_opp_clk_table_vpu3x,
> + /* Upper bound of DMA address range */
> + .dma_mask = 0xe0000000 - 1,
> + .fwname = "qcom/vpu/vpu30_p4.mbn",
> + .inst_iris_fmts = iris_fmts_vpu3x_dec,
> + .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec),
> + .inst_caps = &platform_inst_cap_sm8550,
> + .tz_cp_config_data = tz_cp_config_vpu3,
> + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3),
> + .core_arch = VIDEO_ARCH_LX,
> + .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
> + .num_vpp_pipe = 4,
> + .max_session_count = 16,
> + .max_core_mbpf = NUM_MBS_8K * 2,
> + .max_core_mbps = ((7680 * 4320) / 256) * 60,
> +};
> +
> +/*
> + * Shares most of SM8550 data except:
> + * - vpu_ops to iris_vpu33_ops
> + * - clk_rst_tbl to sm8650_clk_reset_table
> + * - controller_rst_tbl to sm8650_controller_reset_table
> + * - fwname to "qcom/vpu/vpu33_p4.mbn"
> + */
> +const struct iris_platform_data sm8650_data = {
> + .firmware_data = &iris_hfi_gen2_data,
> + .get_vpu_buffer_size = iris_vpu33_buf_size,
> + .vpu_ops = &iris_vpu33_ops,
> + .icc_tbl = iris_icc_info_vpu3x,
> + .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x),
> + .clk_rst_tbl = sm8650_clk_reset_table,
> + .clk_rst_tbl_size = ARRAY_SIZE(sm8650_clk_reset_table),
> + .controller_rst_tbl = sm8650_controller_reset_table,
> + .controller_rst_tbl_size = ARRAY_SIZE(sm8650_controller_reset_table),
> + .bw_tbl_dec = iris_bw_table_dec_vpu3x,
> + .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x),
> + .pmdomain_tbl = iris_pmdomain_table_vpu3x,
> + .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu3x),
> + .opp_pd_tbl = iris_opp_pd_table_vpu3x,
> + .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x),
> + .clk_tbl = sm8550_clk_table,
> + .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
> + .opp_clk_tbl = iris_opp_clk_table_vpu3x,
> + /* Upper bound of DMA address range */
> + .dma_mask = 0xe0000000 - 1,
> + .fwname = "qcom/vpu/vpu33_p4.mbn",
> + .inst_iris_fmts = iris_fmts_vpu3x_dec,
> + .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec),
> + .inst_caps = &platform_inst_cap_sm8550,
> + .tz_cp_config_data = tz_cp_config_vpu3,
> + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3),
> + .core_arch = VIDEO_ARCH_LX,
> + .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
> + .num_vpp_pipe = 4,
> + .max_session_count = 16,
> + .max_core_mbpf = NUM_MBS_8K * 2,
> + .max_core_mbps = ((7680 * 4320) / 256) * 60,
> +};
> +
> +const struct iris_platform_data sm8750_data = {
> + .firmware_data = &iris_hfi_gen2_data,
> + .get_vpu_buffer_size = iris_vpu33_buf_size,
> + .vpu_ops = &iris_vpu35_ops,
> + .icc_tbl = iris_icc_info_vpu3x,
> + .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x),
> + .clk_rst_tbl = sm8750_clk_reset_table,
> + .clk_rst_tbl_size = ARRAY_SIZE(sm8750_clk_reset_table),
> + .bw_tbl_dec = iris_bw_table_dec_vpu3x,
> + .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x),
> + .pmdomain_tbl = iris_pmdomain_table_vpu3x,
> + .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu3x),
> + .opp_pd_tbl = iris_opp_pd_table_vpu3x,
> + .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x),
> + .clk_tbl = sm8750_clk_table,
> + .clk_tbl_size = ARRAY_SIZE(sm8750_clk_table),
> + .opp_clk_tbl = iris_opp_clk_table_vpu3x,
> + /* Upper bound of DMA address range */
> + .dma_mask = 0xe0000000 - 1,
> + .fwname = "qcom/vpu/vpu35_p4.mbn",
> + .inst_iris_fmts = iris_fmts_vpu3x_dec,
> + .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec),
> + .inst_caps = &platform_inst_cap_sm8550,
> + .tz_cp_config_data = tz_cp_config_vpu3,
> + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3),
> + .core_arch = VIDEO_ARCH_LX,
> + .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
> + .num_vpp_pipe = 4,
> + .max_session_count = 16,
> + .max_core_mbpf = NUM_MBS_8K * 2,
> + .max_core_mbps = ((7680 * 4320) / 256) * 60,
> +};
>
next prev parent reply other threads:[~2026-03-18 10:26 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-16 18:54 [PATCH v7 0/8] media: qcom: iris: rework platform data handling Dmitry Baryshkov
2026-03-16 18:54 ` [PATCH v7 1/8] media: qcom: iris: drop pas_id from the iris_platform_data struct Dmitry Baryshkov
2026-03-18 11:01 ` Vikash Garodia
2026-03-16 18:54 ` [PATCH v7 2/8] media: qcom: iris: use common set_preset_registers function Dmitry Baryshkov
2026-03-18 11:01 ` Vikash Garodia
2026-03-16 18:54 ` [PATCH v7 3/8] media: qcom: iris: don't use function indirection in gen2-specific code Dmitry Baryshkov
2026-03-18 11:03 ` Vikash Garodia
2026-03-16 18:54 ` [PATCH v7 4/8] media: qcom: iris: split HFI session ops from core ops Dmitry Baryshkov
2026-03-18 11:31 ` Vikash Garodia
2026-03-16 18:54 ` [PATCH v7 5/8] media: qcom: iris: merge hfi_response_ops and hfi_command_ops Dmitry Baryshkov
2026-03-18 11:38 ` Vikash Garodia
2026-03-16 18:54 ` [PATCH v7 6/8] media: qcom: iris: move get_instance to iris_hfi_sys_ops Dmitry Baryshkov
2026-03-18 11:39 ` Vikash Garodia
2026-03-16 18:54 ` [PATCH v7 7/8] media: qcom: iris: split firmware_data from raw platform data Dmitry Baryshkov
2026-03-18 9:05 ` Dikshita Agarwal
2026-03-18 10:29 ` Dmitry Baryshkov
2026-03-18 10:33 ` Dikshita Agarwal
2026-03-18 10:40 ` Dmitry Baryshkov
2026-03-18 10:42 ` Dikshita Agarwal
2026-03-18 13:42 ` Dmitry Baryshkov
2026-03-16 18:54 ` [PATCH v7 8/8] media: qcom: iris: split platform data from firmware data Dmitry Baryshkov
2026-03-18 10:26 ` Vikash Garodia [this message]
2026-03-18 13:52 ` Vikash Garodia
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