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From: Ravi Bangoria <ravi.bangoria@amd.com>
To: Hang Zhengyang <hang.zhengyang1010@gmail.com>,
	Jacob Lefkowitz <jlefkowi@akamai.com>,
	Vasant Hegde <vasant.hegde@amd.com>
Cc: Peter Zijlstra <peterz@infradead.org>,
	Ingo Molnar <mingo@redhat.com>,
	Arnaldo Carvalho de Melo <acme@kernel.org>,
	Namhyung Kim <namhyung@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	"Alexander Shishkin" <alexander.shishkin@linux.intel.com>,
	Jiri Olsa <jolsa@kernel.org>, Ian Rogers <irogers@google.com>,
	Adrian Hunter <adrian.hunter@intel.com>,
	James Clark <james.clark@linaro.org>,
	Ben Chaney <bchaney@akamai.com>,
	"Matt Pelland" <mpelland@akamai.com>,
	<linux-perf-users@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 0/2] perf jevents: Add IOMMU PTW & device entry metrics
Date: Sat, 14 Nov 2026 08:59:41 +0530	[thread overview]
Message-ID: <c52fb4b3-1b9a-40ff-ad6f-5d2325443a73@amd.com> (raw)
In-Reply-To: <20261110032232.3080268-1-hang.zhengyang1010@gmail.com>

On 10-Nov-26 8:52 AM, Hang Zhengyang wrote:
> [You don't often get email from hang.zhengyang1010@gmail.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> 
> On Mon, 02 Nov 2026 21:14:15 +0000, Jacob Lefkowitz wrote:
>> Adds AMD specific metrics for the IOMMU with respect to page table
>> walks and device table entires.
> 
> Tested on Zen 3 (Ryzen 7 PRO 5850U) on top of perf-tools-next
> 13a8d580433a.  Both groups show up and count, perf test 130 and 131
> pass, and under O_DIRECT reads from NVMe the values match the raw
> amd_iommu_0 counts.
> 
> Tested-by: Hang Zhengyang <hang.zhengyang1010@gmail.com>
> 
> Two values look odd on this machine:
> 
>  - lpm_iommu_ptw_nested_read_ratio is 100% with no guest running:
>    page_tbl_read_nst equals page_tbl_read_tot.
> 
>  - lpm_iommu_ptw_reads_per_tlb_miss is about 0.2: 142588 page table
>    reads against 440805 pte and 192018 pde misses.
> 
> Ravi, are these expected on Zen 3?
> 
> (Tested with the help of an AI assistant; I checked the results.)

Adding Vasant, as he is more familiar with the IOMMU PMU area.

      reply	other threads:[~2026-11-14  3:30 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-02 21:14 Jacob Lefkowitz via B4 Relay
2026-11-02 21:14 ` [PATCH v2 1/2] perf jevents: add iommu page table walk metrics Jacob Lefkowitz via B4 Relay
2026-11-02 21:14 ` [PATCH v2 2/2] perf jevents: add amd specific device table entry metrics Jacob Lefkowitz via B4 Relay
2026-11-10  3:22 ` [PATCH v2 0/2] perf jevents: Add IOMMU PTW & device " Hang Zhengyang
2026-11-14  3:29   ` Ravi Bangoria [this message]

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