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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by MWH0EPF000989EB.mail.protection.outlook.com (10.167.241.138) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9520.1 via Frontend Transport; Thu, 8 Jan 2026 17:52:19 +0000 Received: from satlexmb08.amd.com (10.181.42.217) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Thu, 8 Jan 2026 11:52:19 -0600 Received: from [172.19.71.207] (10.180.168.240) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Thu, 8 Jan 2026 11:52:19 -0600 Message-ID: Date: Thu, 8 Jan 2026 09:52:18 -0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH V1 2/2] accel/amdxdna: Update firmware version check for latest firmware Content-Language: en-US To: "Mario Limonciello (AMD) (kernel.org)" , , , , CC: , , References: <20251219014356.2234241-1-lizhi.hou@amd.com> <20251219014356.2234241-2-lizhi.hou@amd.com> <0eb1b06c-72be-409b-b49a-e340bf49453d@amd.com> <2cb7bd75-79b8-1a45-8945-0e86f86ede08@amd.com> From: Lizhi Hou In-Reply-To: Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jan 2026 17:52:19.9555 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 76fd1b30-ff86-4c17-0fc7-08de4edeab8b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000989EB.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB8178 Applied to drm-misc-next. On 1/7/26 19:26, Mario Limonciello (AMD) (kernel.org) wrote: > > > On 1/7/2026 4:12 PM, Lizhi Hou wrote: >> >> On 1/7/26 13:20, Mario Limonciello wrote: >>> On 12/18/25 7:43 PM, Lizhi Hou wrote: >>>> The latest firmware increases the major version number. Update >>>> aie2_check_protocol() to accept and support the new firmware version. >>>> >>>> Signed-off-by: Lizhi Hou >>> >>> I know it's painful and tech debt; but I suggest you add new paths >>> to handle both versions of firmware at least until the next LTS kernel. >> >> With the patch 1, the driver works fine for both current firmware and >> upcoming firmware. >> >> Lizhi >> > > Thank for confirming, no other concerns with this patch. > > Reviewed-by: Mario Limonciello (AMD) > >>> >>>> --- >>>>   drivers/accel/amdxdna/aie2_pci.c  | 36 >>>> ++++++++----------------------- >>>>   drivers/accel/amdxdna/aie2_pci.h  |  5 ++--- >>>>   drivers/accel/amdxdna/npu1_regs.c |  6 +++--- >>>>   drivers/accel/amdxdna/npu4_regs.c | 11 +++++----- >>>>   drivers/accel/amdxdna/npu5_regs.c |  2 -- >>>>   drivers/accel/amdxdna/npu6_regs.c |  2 -- >>>>   6 files changed, 20 insertions(+), 42 deletions(-) >>>> >>>> diff --git a/drivers/accel/amdxdna/aie2_pci.c b/drivers/accel/ >>>> amdxdna/aie2_pci.c >>>> index 81a8e4137bfd..181fdbc10dae 100644 >>>> --- a/drivers/accel/amdxdna/aie2_pci.c >>>> +++ b/drivers/accel/amdxdna/aie2_pci.c >>>> @@ -56,41 +56,23 @@ struct mgmt_mbox_chann_info { >>>>   static int aie2_check_protocol(struct amdxdna_dev_hdl *ndev, u32 >>>> fw_major, u32 fw_minor) >>>>   { >>>>       const struct aie2_fw_feature_tbl *feature; >>>> -    struct amdxdna_dev *xdna = ndev->xdna; >>>> - >>>> -    /* >>>> -     * The driver supported mailbox behavior is defined by >>>> -     * ndev->priv->protocol_major and protocol_minor. >>>> -     * >>>> -     * When protocol_major and fw_major are different, it means >>>> driver >>>> -     * and firmware are incompatible. >>>> -     */ >>>> -    if (ndev->priv->protocol_major != fw_major) { >>>> -        XDNA_ERR(xdna, "Incompatible firmware protocol major %d >>>> minor %d", >>>> -             fw_major, fw_minor); >>>> -        return -EINVAL; >>>> -    } >>>> +    bool found = false; >>>>   -    /* >>>> -     * When protocol_minor is greater then fw_minor, that means >>>> driver >>>> -     * relies on operation the installed firmware does not support. >>>> -     */ >>>> -    if (ndev->priv->protocol_minor > fw_minor) { >>>> -        XDNA_ERR(xdna, "Firmware minor version smaller than >>>> supported"); >>>> -        return -EINVAL; >>>> -    } >>>> - >>>> -    for (feature = ndev->priv->fw_feature_tbl; feature && feature- >>>> >min_minor; >>>> -         feature++) { >>>> +    for (feature = ndev->priv->fw_feature_tbl; feature->major; >>>> feature++) { >>>> +        if (feature->major != fw_major) >>>> +            continue; >>>>           if (fw_minor < feature->min_minor) >>>>               continue; >>>>           if (feature->max_minor > 0 && fw_minor > feature->max_minor) >>>>               continue; >>>>   -        set_bit(feature->feature, &ndev->feature_mask); >>>> +        ndev->feature_mask |= feature->features; >>>> + >>>> +        /* firmware version matches one of the driver support >>>> entry */ >>>> +        found = true; >>>>       } >>>>   -    return 0; >>>> +    return found ? 0 : -EOPNOTSUPP; >>>>   } >>>>     static void aie2_dump_chann_info_debug(struct amdxdna_dev_hdl >>>> *ndev) >>>> diff --git a/drivers/accel/amdxdna/aie2_pci.h b/drivers/accel/ >>>> amdxdna/aie2_pci.h >>>> index e1745f07b268..b20a3661078c 100644 >>>> --- a/drivers/accel/amdxdna/aie2_pci.h >>>> +++ b/drivers/accel/amdxdna/aie2_pci.h >>>> @@ -237,7 +237,8 @@ enum aie2_fw_feature { >>>>   }; >>>>     struct aie2_fw_feature_tbl { >>>> -    enum aie2_fw_feature feature; >>>> +    u64 features; >>>> +    u32 major; >>>>       u32 max_minor; >>>>       u32 min_minor; >>>>   }; >>>> @@ -246,8 +247,6 @@ struct aie2_fw_feature_tbl { >>>>     struct amdxdna_dev_priv { >>>>       const char            *fw_path; >>>> -    u64                protocol_major; >>>> -    u64                protocol_minor; >>>>       const struct rt_config        *rt_config; >>>>       const struct dpm_clk_freq    *dpm_clk_tbl; >>>>       const struct aie2_fw_feature_tbl *fw_feature_tbl; >>>> diff --git a/drivers/accel/amdxdna/npu1_regs.c b/drivers/accel/ >>>> amdxdna/npu1_regs.c >>>> index ebc6e2802297..6f36a27b5a02 100644 >>>> --- a/drivers/accel/amdxdna/npu1_regs.c >>>> +++ b/drivers/accel/amdxdna/npu1_regs.c >>>> @@ -6,6 +6,7 @@ >>>>   #include >>>>   #include >>>>   #include >>>> +#include >>>>   #include >>>>     #include "aie2_pci.h" >>>> @@ -65,14 +66,13 @@ const struct dpm_clk_freq npu1_dpm_clk_table[] = { >>>>   }; >>>>     static const struct aie2_fw_feature_tbl npu1_fw_feature_table[] >>>> = { >>>> -    { .feature = AIE2_NPU_COMMAND, .min_minor = 8 }, >>>> +    { .major = 5, .min_minor = 7 }, >>>> +    { .features = BIT_U64(AIE2_NPU_COMMAND), .min_minor = 8 }, >>>>       { 0 } >>>>   }; >>>>     static const struct amdxdna_dev_priv npu1_dev_priv = { >>>>       .fw_path        = "amdnpu/1502_00/npu.sbin", >>>> -    .protocol_major = 0x5, >>>> -    .protocol_minor = 0x7, >>>>       .rt_config    = npu1_default_rt_cfg, >>>>       .dpm_clk_tbl    = npu1_dpm_clk_table, >>>>       .fw_feature_tbl = npu1_fw_feature_table, >>>> diff --git a/drivers/accel/amdxdna/npu4_regs.c b/drivers/accel/ >>>> amdxdna/npu4_regs.c >>>> index a62234fd266d..a8d6f76dde5f 100644 >>>> --- a/drivers/accel/amdxdna/npu4_regs.c >>>> +++ b/drivers/accel/amdxdna/npu4_regs.c >>>> @@ -6,6 +6,7 @@ >>>>   #include >>>>   #include >>>>   #include >>>> +#include >>>>   #include >>>>     #include "aie2_pci.h" >>>> @@ -88,16 +89,16 @@ const struct dpm_clk_freq npu4_dpm_clk_table[] = { >>>>   }; >>>>     const struct aie2_fw_feature_tbl npu4_fw_feature_table[] = { >>>> -    { .feature = AIE2_NPU_COMMAND, .min_minor = 15 }, >>>> -    { .feature = AIE2_PREEMPT, .min_minor = 12 }, >>>> -    { .feature = AIE2_TEMPORAL_ONLY, .min_minor = 12 }, >>>> +    { .major = 6, .min_minor = 12 }, >>>> +    { .features = BIT_U64(AIE2_NPU_COMMAND), .major = 6, >>>> .min_minor = 15 }, >>>> +    { .features = BIT_U64(AIE2_PREEMPT), .major = 6, .min_minor = >>>> 12 }, >>>> +    { .features = BIT_U64(AIE2_TEMPORAL_ONLY), .major = 6, >>>> .min_minor = 12 }, >>>> +    { .features = GENMASK_ULL(AIE2_TEMPORAL_ONLY, >>>> AIE2_NPU_COMMAND), .major = 7 }, >>>>       { 0 } >>>>   }; >>>>     static const struct amdxdna_dev_priv npu4_dev_priv = { >>>>       .fw_path        = "amdnpu/17f0_10/npu.sbin", >>>> -    .protocol_major = 0x6, >>>> -    .protocol_minor = 12, >>>>       .rt_config    = npu4_default_rt_cfg, >>>>       .dpm_clk_tbl    = npu4_dpm_clk_table, >>>>       .fw_feature_tbl = npu4_fw_feature_table, >>>> diff --git a/drivers/accel/amdxdna/npu5_regs.c b/drivers/accel/ >>>> amdxdna/npu5_regs.c >>>> index 131080652ef0..c0a35cfd886c 100644 >>>> --- a/drivers/accel/amdxdna/npu5_regs.c >>>> +++ b/drivers/accel/amdxdna/npu5_regs.c >>>> @@ -64,8 +64,6 @@ >>>>     static const struct amdxdna_dev_priv npu5_dev_priv = { >>>>       .fw_path        = "amdnpu/17f0_11/npu.sbin", >>>> -    .protocol_major = 0x6, >>>> -    .protocol_minor = 12, >>>>       .rt_config    = npu4_default_rt_cfg, >>>>       .dpm_clk_tbl    = npu4_dpm_clk_table, >>>>       .fw_feature_tbl = npu4_fw_feature_table, >>>> diff --git a/drivers/accel/amdxdna/npu6_regs.c b/drivers/accel/ >>>> amdxdna/npu6_regs.c >>>> index 1f71285655b2..1fb07df99186 100644 >>>> --- a/drivers/accel/amdxdna/npu6_regs.c >>>> +++ b/drivers/accel/amdxdna/npu6_regs.c >>>> @@ -64,8 +64,6 @@ >>>>     static const struct amdxdna_dev_priv npu6_dev_priv = { >>>>       .fw_path        = "amdnpu/17f0_10/npu.sbin", >>>> -    .protocol_major = 0x6, >>>> -    .protocol_minor = 12, >>>>       .rt_config    = npu4_default_rt_cfg, >>>>       .dpm_clk_tbl    = npu4_dpm_clk_table, >>>>       .fw_feature_tbl = npu4_fw_feature_table, >>> >