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Mon, 29 Jun 2026 07:03:22 -0700 (PDT) X-Received: by 2002:a05:6820:2dd7:b0:6a1:7ed6:9de with SMTP id 006d021491bc7-6a17ed60ad2mr558948eaf.3.1782741801604; Mon, 29 Jun 2026 07:03:21 -0700 (PDT) Received: from [192.168.120.170] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c1250a80b04sm283661766b.34.2026.06.29.07.03.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 29 Jun 2026 07:03:20 -0700 (PDT) Message-ID: Date: Mon, 29 Jun 2026 16:03:18 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 4/4] arm64: dts: qcom: Add IMDT QCS8550 SBC To: William Bright , Manivannan Sadhasivam Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org References: <20260610-imdt-qcs8550-sbc-rfc-v4-0-358e71d606bc@imd-tec.com> <20260610-imdt-qcs8550-sbc-rfc-v4-4-358e71d606bc@imd-tec.com> <8afbc9f9-15ff-4b60-9a0f-845f903d3c9a@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; 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Given that there isn't support > for this IC already in the kernel and that it will take quite a few > weeks/months for me to cobble something together, I am thinking that it > might make sense to drop PCIe support from this patch-series in V5 and > then submit a seperate patch-series with a driver and bindings for this > IC whenever I get something working. Are you OK with this? Sure I'm a bit curious why do you have a switch there in the first place - is there anything else connected to the other port? Would you like for that to be switchable at runtime? +Mani will probably be interested Konrad