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Tue, 21 Jul 2026 12:48:36 -0700 From: Nicolin Chen To: , , CC: , , , , , , , Subject: [PATCH v9 02/12] iommu/arm-smmu-v3: Skip EVTQ/PRIQ setup in kdump kernel Date: Tue, 21 Jul 2026 12:48:11 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023D8:EE_|DS7PR12MB6120:EE_ X-MS-Office365-Filtering-Correlation-Id: 6b8c2a53-612d-4bd7-30d1-08dee7611b5a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|23010399003|36860700016|376014|1800799024|56012099006|11063799006|10067099003|22082099003|18002099003|6133799003; X-Microsoft-Antispam-Message-Info: 5iUDSUQY0gU6K5JLowL1CqK1l+UYdfZvAg4RdoI4CfaYY1TtAQhep4VysKkBEQGquICVB3SC9GpL2BAU9ycVx/o0GX8pef55TpNdYFP1Fj9lsrA5PCf0dD9eUhwTCyqMCMALqHt1/zd22ySQnwiYDZeoYZDM7e5qbV95HGSxHTnmj7amLvUlGmeGTvIPaYrIvAHX4CB2xeIdXFrMhHSZVHD/V3QVaq+KXvaFAUbbdsZVSrxusv/iK2m4yqaqfWrwYV9BkP68civ2ceUJuazpLfMNai1mmZiLTNbdXMJ7JZ3m4Hpra2tgq91AYg/V7pCsY5VeB9txOQrDDV9tUERNebPxCNIr07sVheHw4JleaUR3qKPa8DCQkt/JzFMV074sSxNfXLVkSTTey4LukK0sXYoYy47SUL1xu3TcMxvus6Eo33CvQYU1qdJFjMiovtNg4A0OGp+2Rjf/2kVbODwHcQiafl6n9bQN9DqofhM6RSPtVdB4mzDblKc7uX1iDJa26GUpWyMY62vlBBUVRYbXo7GOS/m9OIlyROlpSk4EUlacguu6CsvFVJdQz/JrqiJTLtdHvhEhtf0cFE2cir8fOBCey6YndhH6Q9koet+wV1l9XkRNDwNBf4r+szowpvmU6U2QS2mXqk6nfgQMtB2F7Bfn3/88mRGORPGPpBRC926VdUq7WcmCsWu0z7RnEwbjzIc/UX3mZI4sCIXyqGrVtw== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(23010399003)(36860700016)(376014)(1800799024)(56012099006)(11063799006)(10067099003)(22082099003)(18002099003)(6133799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: m2yQ5P8FsOdq0DfKNFpy7jnshBsvIfBfidfxwskd3AEefA7NfSYyvPAWoy3xOxth+vZurRRyM5myIaJvCOg27xmrb7DsEhYaGPGOxy1Fjinivl2eoINK4OG5xeUeqaqQX9x2ZUTmPrCjgPROEh+Xm7J1ufheQf40rO8IxedowN3/GmSXbXZ0vAyMipvkwCPtrR5j8IvWg0AIgMuPoOPOs2FQ/qmgUIstbaKlNThkEStgFLFhc0ZTeZnahQVTcbcrEdchoIIbpTWTvHR/L38GMRQkM5O5hDBnQDtC2znLGBKlXdpMrfiJnhv+bmFrfV8yF1Ubsv9reBfPU1c3wL5sFibPqIDpGoyyWtve9c3c813vQQv6JCIGAC/VnMcBtdNy4JMM00rADPPzMxYqAI6Q/58Cz36LFsAyWX9mnjWJRZOOzS7yE7kmv7p3ulCYBS+z X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jul 2026 19:48:58.8569 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6b8c2a53-612d-4bd7-30d1-08dee7611b5a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D8.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6120 In kdump cases, the crashed kernel's CDs and page tables can be corrupted, which could trigger event spamming. Also, we cannot serve page requests. Skip the EVTQ/PRIQ setup entirely rather than enabling then disabling them. Keep the queue allocations themselves, as their Q_MAX_SZ_SHIFT-capped sizes are negligible against a crashkernel reservation. Also add some inline comments explaining that. Suggested-by: Kevin Tian Reviewed-by: Kevin Tian Reviewed-by: Jason Gunthorpe Reviewed-by: Pranjal Shrivastava Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 44 +++++++++++++-------- 1 file changed, 28 insertions(+), 16 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 404790d2c7210..132bee5fbb1d1 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -4821,21 +4821,36 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu) arm_smmu_cmdq_issue_cmd_with_sync( smmu, arm_smmu_make_cmd_op(CMDQ_OP_TLBI_NSNH_ALL)); - /* Event queue */ - writeq_relaxed(smmu->evtq.q.q_base, smmu->base + ARM_SMMU_EVTQ_BASE); - writel_relaxed(smmu->evtq.q.llq.prod, smmu->page1 + ARM_SMMU_EVTQ_PROD); - writel_relaxed(smmu->evtq.q.llq.cons, smmu->page1 + ARM_SMMU_EVTQ_CONS); - - enables |= CR0_EVTQEN; - ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, - ARM_SMMU_CR0ACK); - if (ret) { - dev_err(smmu->dev, "failed to enable event queue\n"); - return ret; + /* + * Event queue + * + * Do not enable in a kdump case, as the crashed kernel's CDs and page + * tables may be corrupted, triggering event spamming. A disabled queue + * simply discards new events, without raising any global error. + */ + if (!is_kdump_kernel()) { + writeq_relaxed(smmu->evtq.q.q_base, + smmu->base + ARM_SMMU_EVTQ_BASE); + writel_relaxed(smmu->evtq.q.llq.prod, + smmu->page1 + ARM_SMMU_EVTQ_PROD); + writel_relaxed(smmu->evtq.q.llq.cons, + smmu->page1 + ARM_SMMU_EVTQ_CONS); + + enables |= CR0_EVTQEN; + ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, + ARM_SMMU_CR0ACK); + if (ret) { + dev_err(smmu->dev, "failed to enable event queue\n"); + return ret; + } } - /* PRI queue */ - if (smmu->features & ARM_SMMU_FEAT_PRI) { + /* + * PRI queue + * + * Do not enable in a kdump case, as we cannot serve page requests. + */ + if (!is_kdump_kernel() && (smmu->features & ARM_SMMU_FEAT_PRI)) { writeq_relaxed(smmu->priq.q.q_base, smmu->base + ARM_SMMU_PRIQ_BASE); writel_relaxed(smmu->priq.q.llq.prod, @@ -4868,9 +4883,6 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu) return ret; } - if (is_kdump_kernel()) - enables &= ~(CR0_EVTQEN | CR0_PRIQEN); - /* Enable the SMMU interface */ enables |= CR0_SMMUEN; ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, -- 2.43.0