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Mon, 18 May 2026 20:39:39 -0700 From: Nicolin Chen To: Will Deacon , Robin Murphy , "Joerg Roedel" , Bjorn Helgaas , "Jason Gunthorpe" CC: "Rafael J . Wysocki" , Len Brown , Pranjal Shrivastava , Mostafa Saleh , Lu Baolu , Kevin Tian , , , , , , , Shuai Xue Subject: [PATCH v4 14/24] iommu/arm-smmu-v3: Introduce per-cmdq cmdq_err_handler callback Date: Mon, 18 May 2026 20:38:57 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF000061C8:EE_|DS2PR12MB9640:EE_ X-MS-Office365-Filtering-Correlation-Id: 9fc3af91-4b75-4e6b-1c68-08deb5584a26 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700016|82310400026|7416014|376014|11063799003|56012099003|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: GdYEmVLrgqWSqLEcjPr7iKILm0RCzf+FkY1dNLTGJH/lMfUdGSOupNhE7ic00Tc56dmQaP3apwUTc8hWkC/sc/+VdUOEQBjJwxZkdnPDMmK6fl76ecdkMjk6AOuarll/9/QKfyDQw+1/zbRK5radqDLZSiTWX0rOpF2H1iKVHpyyA/vHGf4BhsN1JEKD3nS0RjVJJ2jmbKLKTmEOTgOoh1CgT7P9tZi8/8koBVjarxPrP6WywuQj2ybxoYlnYPCbgyFtInvzkOkUnH+dn6a3Vvam5o8E7+P7JPoQ+i8D1Ccx0Za1xjb5mEAQvjxYolJJxt5AfQUwgmAWDrbwC/pp0n5UzTNKuSDn38RNzYs8UWSj3aBL1kXCW9J4uBUGf5bgjpb8+tvHk248Kmwyq4cACoBJgBbAwSQw4kcTgJMK84VvboD/aisrfJeq2XtO2Ms7Iizw61CuCyNtTLEofeKTsKvHadC+2gdvpsavZI61txaSQSNtxcBH1D5MC3Uu1LfyiaVqdS7G4qI530ndYLkvKie0wPXuo7ThvfGT8EM0F5h3OywMqIJi4LjfVLi9Ego6Ri6ANEYSrD/l8KQL6XXLlWMuM0wGkZlD63wh8Mzr2d2/n9z5YhUANVV/z+QuxkEZOJW9z7pVLIrHvGWRy1b+tzsp1ZjU/fgyht8Z3AgHRbRjBYMIWsITHdlnOeXqd2UgSP7zopSLTcezYHX/gBgBjEs6CBGGXlNmaD8qFxzhAbE= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700016)(82310400026)(7416014)(376014)(11063799003)(56012099003)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 4rQbU+yDNy62M8tgmbEn5pzl3pv9yPjC5N0LYXX6iqc2H/jQZqS585SLWcBHy/UyG9xGcNM8pWOaj5NVhMdDlwaxCK4lVOFYIYRzPKAhxUgGxMMjMXj7+9eEQfRw4toTsFRFA8L/0pGQ4Pd2fUntU54VnXPbXxB8UWUPJwKtyfGQSYZvIkuZ2o7Z8tteL0JLIXQ3MI0wXMs6ZWAL2gaGawbRtVonUEltZ1gnZgEZuy/3mEh4yXZL3fiWardFfyVUJ0zi/Btdt0uKc+w9COoky89ayn5rrWMhWvHBfalRYsoTHfIQGsKjh/nh7/9F/41r2dyjAJhgtukZ/KSIv4yk9aR00NE8gPzwk5+c7zSb3poOPfeF6MwRzQKedv5tmUgSPVgAq91wjIu5/aJYAFt6n+2GfA4D2Zz534SQowwz2UuuC6X9ocJYJAKzlYw15XXl X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2026 03:39:53.7467 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9fc3af91-4b75-4e6b-1c68-08deb5584a26 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF000061C8.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS2PR12MB9640 A subsequent change will need arm_smmu_cmdq_issue_cmdlist() to co-clear a pending CMDQ_ERR after a CMD_SYNC poll timeout. And this needs to be done for both smmu->cmdq and tegra241-cmdq. Add a cmdq_err_handler and a paired cmdq_err_lock to struct arm_smmu_cmdq. arm_smmu_gerror_handler() and tegra241_vintf0_handle_error() now take the per-cmdq cmdq_err_lock when acking CMDQ_ERR. tegra241_vintf0_handle_error() also checks (gerror ^ gerrorn) inside the cmdq_err_lock since a concurrent cmdq_err_handler may have already acked the error. arm_smmu_gerror_handler() already covers this via its existing early-exit on no-active-bits. Impl functions and caller will be added in the subsequent change. Assisted-by: Claude:claude-opus-4-7 Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 12 ++++++++++-- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 18 ++++++++++++++---- drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c | 15 ++++++++++++--- 3 files changed, 36 insertions(+), 9 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 46f9e292a1cc8..604f7edf54158 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -695,6 +695,10 @@ struct arm_smmu_queue_poll { bool wfe; }; +struct arm_smmu_cmdq; +typedef void (*arm_smmu_cmdq_err_fn)(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq); + struct arm_smmu_cmdq { struct arm_smmu_queue q; atomic_long_t *valid_map; @@ -702,6 +706,10 @@ struct arm_smmu_cmdq { atomic_t lock; unsigned long *atc_sync_timeouts; bool (*supports_cmd)(struct arm_smmu_cmd *cmd); + + /* Drain a pending CMDQ_ERR; will hold cmdq_err_lock with irqsave */ + arm_smmu_cmdq_err_fn cmdq_err_handler; + raw_spinlock_t cmdq_err_lock; }; static inline bool arm_smmu_cmdq_supports_cmd(struct arm_smmu_cmdq *cmdq, @@ -1163,8 +1171,8 @@ int arm_smmu_init_one_queue(struct arm_smmu_device *smmu, struct arm_smmu_queue *q, void __iomem *page, unsigned long prod_off, unsigned long cons_off, size_t dwords, const char *name); -int arm_smmu_cmdq_init(struct arm_smmu_device *smmu, - struct arm_smmu_cmdq *cmdq); +int arm_smmu_cmdq_init(struct arm_smmu_device *smmu, struct arm_smmu_cmdq *cmdq, + arm_smmu_cmdq_err_fn cmdq_err_handler); static inline bool arm_smmu_master_canwbs(struct arm_smmu_master *master) { diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index d9fe48989fcd7..fc0757359b783 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2255,13 +2255,18 @@ static irqreturn_t arm_smmu_gerror_handler(int irq, void *dev) { u32 gerror, gerrorn, active; struct arm_smmu_device *smmu = dev; + unsigned long flags; + + raw_spin_lock_irqsave(&smmu->cmdq.cmdq_err_lock, flags); gerror = readl_relaxed(smmu->base + ARM_SMMU_GERROR); gerrorn = readl_relaxed(smmu->base + ARM_SMMU_GERRORN); active = gerror ^ gerrorn; - if (!(active & GERROR_ERR_MASK)) + if (!(active & GERROR_ERR_MASK)) { + raw_spin_unlock_irqrestore(&smmu->cmdq.cmdq_err_lock, flags); return IRQ_NONE; /* No errors pending */ + } dev_warn(smmu->dev, "unexpected global error reported (0x%08x), this could be serious\n", @@ -2270,6 +2275,8 @@ static irqreturn_t arm_smmu_gerror_handler(int irq, void *dev) if (active & GERROR_SFM_ERR) { /* SMMU is being disabled, so other errors don't matter */ writel(gerror, smmu->base + ARM_SMMU_GERRORN); + /* Release before arm_smmu_device_disable() that sleeps */ + raw_spin_unlock_irqrestore(&smmu->cmdq.cmdq_err_lock, flags); dev_err(smmu->dev, "device has entered Service Failure Mode!\n"); arm_smmu_device_disable(smmu); return IRQ_HANDLED; @@ -2297,6 +2304,7 @@ static irqreturn_t arm_smmu_gerror_handler(int irq, void *dev) arm_smmu_cmdq_skip_err(smmu); writel(gerror, smmu->base + ARM_SMMU_GERRORN); + raw_spin_unlock_irqrestore(&smmu->cmdq.cmdq_err_lock, flags); return IRQ_HANDLED; } @@ -4357,13 +4365,15 @@ int arm_smmu_init_one_queue(struct arm_smmu_device *smmu, return 0; } -int arm_smmu_cmdq_init(struct arm_smmu_device *smmu, - struct arm_smmu_cmdq *cmdq) +int arm_smmu_cmdq_init(struct arm_smmu_device *smmu, struct arm_smmu_cmdq *cmdq, + arm_smmu_cmdq_err_fn cmdq_err_handler) { unsigned int nents = 1 << cmdq->q.llq.max_n_shift; atomic_set(&cmdq->owner_prod, 0); atomic_set(&cmdq->lock, 0); + raw_spin_lock_init(&cmdq->cmdq_err_lock); + cmdq->cmdq_err_handler = cmdq_err_handler; cmdq->valid_map = (atomic_long_t *)devm_bitmap_zalloc(smmu->dev, nents, GFP_KERNEL); @@ -4389,7 +4399,7 @@ static int arm_smmu_init_queues(struct arm_smmu_device *smmu) if (ret) return ret; - ret = arm_smmu_cmdq_init(smmu, &smmu->cmdq); + ret = arm_smmu_cmdq_init(smmu, &smmu->cmdq, NULL); if (ret) return ret; diff --git a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c index 67be62a6e7640..fb2f8f68fa344 100644 --- a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c +++ b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c @@ -319,10 +319,19 @@ static void tegra241_vintf0_handle_error(struct tegra241_vintf *vintf) while (map) { unsigned long lidx = __ffs64(map); struct tegra241_vcmdq *vcmdq = vintf->lvcmdqs[lidx]; - u32 gerror = readl_relaxed(REG_VCMDQ_PAGE0(vcmdq, GERROR)); + struct arm_smmu_cmdq *cmdq = &vcmdq->cmdq; + unsigned long flags; + u32 gerror, gerrorn; - __arm_smmu_cmdq_skip_err(&vintf->cmdqv->smmu, &vcmdq->cmdq); + raw_spin_lock_irqsave(&cmdq->cmdq_err_lock, flags); + gerror = readl_relaxed(REG_VCMDQ_PAGE0(vcmdq, GERROR)); + gerrorn = readl_relaxed(REG_VCMDQ_PAGE0(vcmdq, GERRORN)); + + if ((gerror ^ gerrorn) & GERROR_CMDQ_ERR) + __arm_smmu_cmdq_skip_err(&vintf->cmdqv->smmu, + cmdq); writel(gerror, REG_VCMDQ_PAGE0(vcmdq, GERRORN)); + raw_spin_unlock_irqrestore(&cmdq->cmdq_err_lock, flags); map &= ~BIT_ULL(lidx); } } @@ -643,7 +652,7 @@ static int tegra241_vcmdq_alloc_smmu_cmdq(struct tegra241_vcmdq *vcmdq) q->q_base = q->base_dma & VCMDQ_ADDR; q->q_base |= FIELD_PREP(VCMDQ_LOG2SIZE, q->llq.max_n_shift); - return arm_smmu_cmdq_init(smmu, cmdq); + return arm_smmu_cmdq_init(smmu, cmdq, NULL); } /* VINTF Logical VCMDQ Resource Helpers */ -- 2.43.0