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> }; > > + display-subsystem { > + compatible = "st,sti-display-subsystem"; > + ports = <&compositor>, <&hqvdp>, <&tvout>, <&sti_hdmi>; > + > + assigned-clocks = <&clk_s_d2_quadfs 0>, > + <&clk_s_d2_quadfs 1>, > + <&clk_s_c0_pll1 0>, > + <&clk_s_c0_flexgen CLK_COMPO_DVP>, > + <&clk_s_c0_flexgen CLK_MAIN_DISP>, > + <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, > + <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, > + <&clk_s_d2_flexgen CLK_PIX_GDP1>, > + <&clk_s_d2_flexgen CLK_PIX_GDP2>, > + <&clk_s_d2_flexgen CLK_PIX_GDP3>, > + <&clk_s_d2_flexgen CLK_PIX_GDP4>; > + > + assigned-clock-parents = <0>, > + <0>, > + <0>, > + <&clk_s_c0_pll1 0>, > + <&clk_s_c0_pll1 0>, > + <&clk_s_d2_quadfs 0>, > + <&clk_s_d2_quadfs 1>, > + <&clk_s_d2_quadfs 0>, > + <&clk_s_d2_quadfs 0>, > + <&clk_s_d2_quadfs 0>, > + <&clk_s_d2_quadfs 0>; > + > + assigned-clock-rates = <297000000>, > + <297000000>, > + <0>, > + <400000000>, > + <400000000>; > + }; > + > soc { > ohci0: usb@9a03c00 { > compatible = "st,st-ohci-300x"; > @@ -99,153 +134,178 @@ ehci1: usb@9a83e00 { > status = "disabled"; > }; > > - sti-display-subsystem@0 { > - compatible = "st,sti-display-subsystem"; > + compositor: display-controller@9d11000 { > + compatible = "st,stih407-compositor"; > + reg = <0x9d11000 0x1000>; > + > + clock-names = "compo_main", > + "compo_aux", > + "pix_main", > + "pix_aux", > + "pix_gdp1", > + "pix_gdp2", > + "pix_gdp3", > + "pix_gdp4", > + "main_parent", > + "aux_parent"; > + > + clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>, > + <&clk_s_c0_flexgen CLK_COMPO_DVP>, > + <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, > + <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, > + <&clk_s_d2_flexgen CLK_PIX_GDP1>, > + <&clk_s_d2_flexgen CLK_PIX_GDP2>, > + <&clk_s_d2_flexgen CLK_PIX_GDP3>, > + <&clk_s_d2_flexgen CLK_PIX_GDP4>, > + <&clk_s_d2_quadfs 0>, > + <&clk_s_d2_quadfs 1>; > + > + reset-names = "compo-main", "compo-aux"; > + resets = <&softreset STIH407_COMPO_SOFTRESET>, > + <&softreset STIH407_COMPO_SOFTRESET>; > + st,vtg = <&vtg_main>, <&vtg_aux>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + compo_main_out: endpoint { > + remote-endpoint = <&tvout_in0>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + compo_aux_out: endpoint { > + remote-endpoint = <&tvout_in1>; > + }; > + }; > + }; > + }; > + > + tvout: encoder@8d08000 { > + compatible = "st,stih407-tvout"; > + reg = <0x8d08000 0x1000>; > + reg-names = "tvout-reg"; > + reset-names = "tvout"; > + resets = <&softreset STIH407_HDTVOUT_SOFTRESET>; > #address-cells = <1>; > #size-cells = <1>; > + assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, > + <&clk_s_d2_flexgen CLK_TMDS_HDMI>, > + <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, > + <&clk_s_d0_flexgen CLK_PCM_0>, > + <&clk_s_d2_flexgen CLK_PIX_HDDAC>, > + <&clk_s_d2_flexgen CLK_HDDAC>; > > - reg = <0 0>; > - assigned-clocks = <&clk_s_d2_quadfs 0>, > - <&clk_s_d2_quadfs 1>, > - <&clk_s_c0_pll1 0>, > - <&clk_s_c0_flexgen CLK_COMPO_DVP>, > - <&clk_s_c0_flexgen CLK_MAIN_DISP>, > - <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, > - <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, > - <&clk_s_d2_flexgen CLK_PIX_GDP1>, > - <&clk_s_d2_flexgen CLK_PIX_GDP2>, > - <&clk_s_d2_flexgen CLK_PIX_GDP3>, > - <&clk_s_d2_flexgen CLK_PIX_GDP4>; > - > - assigned-clock-parents = <0>, > - <0>, > - <0>, > - <&clk_s_c0_pll1 0>, > - <&clk_s_c0_pll1 0>, > - <&clk_s_d2_quadfs 0>, > - <&clk_s_d2_quadfs 1>, > - <&clk_s_d2_quadfs 0>, > + assigned-clock-parents = <&clk_s_d2_quadfs 0>, > + <&clk_tmdsout_hdmi>, > <&clk_s_d2_quadfs 0>, > + <&clk_s_d0_quadfs 0>, > <&clk_s_d2_quadfs 0>, > <&clk_s_d2_quadfs 0>; > > - assigned-clock-rates = <297000000>, > - <297000000>, > - <0>, > - <400000000>, > - <400000000>; > - > - ranges; > - > - sti-compositor@9d11000 { > - compatible = "st,stih407-compositor"; > - reg = <0x9d11000 0x1000>; > - > - clock-names = "compo_main", > - "compo_aux", > - "pix_main", > - "pix_aux", > - "pix_gdp1", > - "pix_gdp2", > - "pix_gdp3", > - "pix_gdp4", > - "main_parent", > - "aux_parent"; > - > - clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>, > - <&clk_s_c0_flexgen CLK_COMPO_DVP>, > - <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, > - <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, > - <&clk_s_d2_flexgen CLK_PIX_GDP1>, > - <&clk_s_d2_flexgen CLK_PIX_GDP2>, > - <&clk_s_d2_flexgen CLK_PIX_GDP3>, > - <&clk_s_d2_flexgen CLK_PIX_GDP4>, > - <&clk_s_d2_quadfs 0>, > - <&clk_s_d2_quadfs 1>; > - > - reset-names = "compo-main", "compo-aux"; > - resets = <&softreset STIH407_COMPO_SOFTRESET>, > - <&softreset STIH407_COMPO_SOFTRESET>; > - st,vtg = <&vtg_main>, <&vtg_aux>; > - }; > - > - sti-tvout@8d08000 { > - compatible = "st,stih407-tvout"; > - reg = <0x8d08000 0x1000>; > - reg-names = "tvout-reg"; > - reset-names = "tvout"; > - resets = <&softreset STIH407_HDTVOUT_SOFTRESET>; > + ports { > #address-cells = <1>; > - #size-cells = <1>; > - assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, > - <&clk_s_d2_flexgen CLK_TMDS_HDMI>, > - <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, > - <&clk_s_d0_flexgen CLK_PCM_0>, > - <&clk_s_d2_flexgen CLK_PIX_HDDAC>, > - <&clk_s_d2_flexgen CLK_HDDAC>; > + #size-cells = <0>; > > - assigned-clock-parents = <&clk_s_d2_quadfs 0>, > - <&clk_tmdsout_hdmi>, > - <&clk_s_d2_quadfs 0>, > - <&clk_s_d0_quadfs 0>, > - <&clk_s_d2_quadfs 0>, > - <&clk_s_d2_quadfs 0>; > + port@0 { > + reg = <0>; > + tvout_in0: endpoint { > + remote-endpoint = <&compo_main_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + tvout_in1: endpoint { > + remote-endpoint = <&compo_aux_out>; > + }; > + }; > + > + port@2 { > + reg = <2>; > + tvout_out0: endpoint { > + remote-endpoint = <&hdmi_in>; > + }; > + }; > + > + port@3 { > + reg = <3>; > + tvout_out1: endpoint { > + remote-endpoint = <&hda_in>; > + }; > + }; > }; > + }; > > - sti_hdmi: sti-hdmi@8d04000 { > - compatible = "st,stih407-hdmi"; > - reg = <0x8d04000 0x1000>; > - reg-names = "hdmi-reg"; > - #sound-dai-cells = <0>; > - interrupts = ; > - interrupt-names = "irq"; > - clock-names = "pix", > - "tmds", > - "phy", > - "audio", > - "main_parent", > - "aux_parent"; > + sti_hdmi: hdmi@8d04000 { > + compatible = "st,stih407-hdmi"; > + reg = <0x8d04000 0x1000>; > + reg-names = "hdmi-reg"; > + #sound-dai-cells = <0>; > + interrupts = ; > + interrupt-names = "irq"; > + clock-names = "pix", > + "tmds", > + "phy", > + "audio", > + "main_parent", > + "aux_parent"; > > - clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, > - <&clk_s_d2_flexgen CLK_TMDS_HDMI>, > - <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, > - <&clk_s_d0_flexgen CLK_PCM_0>, > - <&clk_s_d2_quadfs 0>, > - <&clk_s_d2_quadfs 1>; > + clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, > + <&clk_s_d2_flexgen CLK_TMDS_HDMI>, > + <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, > + <&clk_s_d0_flexgen CLK_PCM_0>, > + <&clk_s_d2_quadfs 0>, > + <&clk_s_d2_quadfs 1>; > > - hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>; > - reset-names = "hdmi"; > - resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>; > - ddc = <&hdmiddc>; > + hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>; > + reset-names = "hdmi"; > + resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>; > + ddc = <&hdmiddc>; > + > + port { > + hdmi_in: endpoint { > + remote-endpoint = <&tvout_out0>; > + }; > }; > + }; > > - sti-hda@8d02000 { > - compatible = "st,stih407-hda"; > - status = "disabled"; > - reg = <0x8d02000 0x400>, <0x92b0120 0x4>; > - reg-names = "hda-reg", "video-dacs-ctrl"; > - clock-names = "pix", > - "hddac", > - "main_parent", > - "aux_parent"; > - clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>, > - <&clk_s_d2_flexgen CLK_HDDAC>, > - <&clk_s_d2_quadfs 0>, > - <&clk_s_d2_quadfs 1>; > - }; > + analog@8d02000 { > + compatible = "st,stih407-hda"; > + status = "disabled"; > + reg = <0x8d02000 0x400>, <0x92b0120 0x4>; > + reg-names = "hda-reg", "video-dacs-ctrl"; > + clock-names = "pix", > + "hddac", > + "main_parent", > + "aux_parent"; > + clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>, > + <&clk_s_d2_flexgen CLK_HDDAC>, > + <&clk_s_d2_quadfs 0>, > + <&clk_s_d2_quadfs 1>; > > - sti-hqvdp@9c00000 { > - compatible = "st,stih407-hqvdp"; > - reg = <0x9C00000 0x100000>; > - clock-names = "hqvdp", "pix_main"; > - clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>, > - <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>; > - reset-names = "hqvdp"; > - resets = <&softreset STIH407_HDQVDP_SOFTRESET>; > - st,vtg = <&vtg_main>; > + port { > + hda_in: endpoint { > + remote-endpoint = <&tvout_out1>; > + }; > }; > }; > > + hqvdp: plane@9c00000 { > + compatible = "st,stih407-hqvdp"; > + reg = <0x9C00000 0x100000>; > + clock-names = "hqvdp", "pix_main"; > + clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>, > + <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>; > + reset-names = "hqvdp"; > + resets = <&softreset STIH407_HDQVDP_SOFTRESET>; > + st,vtg = <&vtg_main>; > + }; > + > bdisp0:bdisp@9f10000 { > compatible = "st,stih407-bdisp"; > reg = <0x9f10000 0x1000>; > Acked-by: Patrice Chotard Thanks PAtrice