Re: [PATCH 1/2] dt-bindings: interrupt-controller: introduce toshiba,tc9564-msigen.yaml

[Krzysztof Kozlowski <krzk@kernel.org>]

On 14/10/2026 12:15, Krzysztof Kozlowski wrote:
> On Tue, Oct 13, 2026 at 06:54:11PM +0100, Conor Dooley wrote:
>> On Mon, Oct 12, 2026 at 02:02:43PM -0500, Alex Elder wrote:
>>> Define the binding for the MSIGEN interrupt controller present in the
>>> Toshiba TC9564 SoC.
>>>
>>> Co-developed-by: Daniel Thompson <daniel@riscstar.com>
>>> Signed-off-by: Daniel Thompson <daniel@riscstar.com>
>>> Signed-off-by: Alex Elder <elder@riscstar.com>
>>> ---
>>>  .../toshiba,tc9564-msigen.yaml                | 70 +++++++++++++++++++
>>>  MAINTAINERS                                   |  6 ++
>>>  2 files changed, 76 insertions(+)
>>>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/toshiba,tc9564-msigen.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/toshiba,tc9564-msigen.yaml b/Documentation/devicetree/bindings/interrupt-controller/toshiba,tc9564-msigen.yaml
>>> new file mode 100644
>>> index 0000000000000..39dc63964bd52
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/interrupt-controller/toshiba,tc9564-msigen.yaml
>>> @@ -0,0 +1,70 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/interrupt-controller/toshiba,tc9564-msigen.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Toshiba TC9564 MSIGEN Interrupt Controller
>>> +
>>> +maintainers:
>>> +  - Daniel Thompson <daniel@riscstar.com>
>>> +  - Alex Elder <elder@riscstar.com>
>>> +
>>> +description: |
>>> +  The Toshiba TC9564 is an SoC accessed by a host system through the
>>> +  upstream PCIe port on the PCIe switch it implements.  The switch
>>> +  includes an embedded PCIe endpoint that provides access to various
>>> +  SoC peripherals (including an interrupt controller) via its BARs.
>>> +
>>> +  The TC9564 MSIGEN (MSI Generator) provides an interrupt controller
>>> +  with 25 hardware interrupt lines.  It aggregates internal interrupts
>>> +  and generates a single PCIe MSI to the host.  Each PCIe function
>>> +  implements an MSIGEN instance.
>>> +
>>> +  Each MSIGEN uses a gated clock and reset line.  These are provided
>>> +  by the clock and reset controllers internal to the TC9564.
>>> +
>>> +allOf:
>>> +  - $ref: /schemas/interrupt-controller.yaml#
>>> +
>>> +properties:
>>> +  compatible:
>>> +    const: toshiba,tc9564-msigen
>>> +
>>> +  reg:
>>> +    maxItems: 1
>>> +
>>> +  interrupt-controller: true
>>> +
>>> +  '#interrupt-cells':
>>> +    const: 1
>>> +
>>> +  clocks:
>>> +    maxItems: 1
>>> +    description: Gate clock from the TC9564 clock controller
>>
>> I'm surprised that the clock is not mandatory.. Realistically the reset
>> is also mandatory, there's probably one instance of this on the device,
>> where both clock and reset are connected. I'd add both to the required
>> list.
>>
>> Otherwise this looks
>> fine to me. I know you mentioned this device in the other series that
>> we were discussing but I don't see how it is related and is perfectly
>> fine to implement as a standalone device as you have done here.
> 
> I still do not understand why do we need to describe the inner wirings
> of the tc9564 device. So far I found no posting of DTS showing proper
> usage of it on the host. Without proper usage, what is the point exactly
> to describe the inner specifics of tc9564?

And as shown here:
https://lore.kernel.org/all/20261012152408.3729237-5-elder@riscstar.com/

there is no single user of any of this (this=reset, clock, irqchip
probably and more) in upstreamed patches.

I am getting tired to keep discussing it, so next time instead of words,
please post CODE which is the argument - who uses any of these devices
you keep adding.

Best regards,
Krzysztof