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Sun, 23 Feb 2025 23:04:53 -0800 (PST) X-Google-Smtp-Source: AGHT+IEb5MhpjJCIMzKcXsJRwIio6H1DsGvFgoeETQaOrh0qyse+TUhBysl2xMdsD1dadgJePi5zyg== X-Received: by 2002:a17:902:b205:b0:220:ff3f:6cbc with SMTP id d9443c01a7336-221a1148e8emr150627665ad.34.1740380692729; Sun, 23 Feb 2025 23:04:52 -0800 (PST) Received: from [10.92.199.34] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-220d55866ecsm173253775ad.212.2025.02.23.23.04.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 23 Feb 2025 23:04:52 -0800 (PST) Message-ID: Date: Mon, 24 Feb 2025 12:34:45 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v6 4/4] PCI: dwc: Add support for configuring lane equalization presets Content-Language: en-US To: Manivannan Sadhasivam Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Jingoo Han , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, quic_mrana@quicinc.com, quic_vbadigan@quicinc.com References: <20250210-preset_v6-v6-0-cbd837d0028d@oss.qualcomm.com> <20250210-preset_v6-v6-4-cbd837d0028d@oss.qualcomm.com> <20250214093414.pvx6nab7ewy4nvzb@thinkpad> From: Krishna Chaitanya Chundru In-Reply-To: <20250214093414.pvx6nab7ewy4nvzb@thinkpad> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: BNjrN988FkDwCH48O-jia7wpHnfBxl9m X-Proofpoint-ORIG-GUID: BNjrN988FkDwCH48O-jia7wpHnfBxl9m X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-24_02,2025-02-20_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 adultscore=0 phishscore=0 mlxlogscore=977 spamscore=0 mlxscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2502240050 On 2/14/2025 3:04 PM, Manivannan Sadhasivam wrote: > On Mon, Feb 10, 2025 at 01:00:03PM +0530, Krishna Chaitanya Chundru wrote: >> PCIe equalization presets are predefined settings used to optimize >> signal integrity by compensating for signal loss and distortion in >> high-speed data transmission. >> >> Based upon the number of lanes and the data rate supported, write >> the preset data read from the device tree in to the lane equalization >> control registers. >> >> Signed-off-by: Krishna Chaitanya Chundru >> --- >> drivers/pci/controller/dwc/pcie-designware-host.c | 53 +++++++++++++++++++++++ >> drivers/pci/controller/dwc/pcie-designware.h | 3 ++ >> include/uapi/linux/pci_regs.h | 3 ++ >> 3 files changed, 59 insertions(+) >> >> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c >> index dd56cc02f4ef..7d5f16f77e2f 100644 >> --- a/drivers/pci/controller/dwc/pcie-designware-host.c >> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c >> @@ -507,6 +507,10 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) >> if (pci->num_lanes < 1) >> pci->num_lanes = dw_pcie_link_get_max_link_width(pci); >> >> + ret = of_pci_get_equalization_presets(dev, &pp->presets, pci->num_lanes); >> + if (ret) >> + goto err_free_msi; >> + >> /* >> * Allocate the resource for MSG TLP before programming the iATU >> * outbound window in dw_pcie_setup_rc(). Since the allocation depends >> @@ -808,6 +812,54 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) >> return 0; >> } >> >> +static void dw_pcie_program_presets(struct dw_pcie_rp *pp, enum pci_bus_speed speed) >> +{ >> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); >> + u8 lane_eq_offset, lane_reg_size, cap_id; >> + u8 *presets; >> + u32 cap; >> + int i; >> + >> + if (speed == PCIE_SPEED_8_0GT) { >> + presets = (u8 *)pp->presets.eq_presets_8gts; >> + lane_eq_offset = PCI_SECPCI_LE_CTRL; >> + cap_id = PCI_EXT_CAP_ID_SECPCI; >> + /* For data rate of 8 GT/S each lane equalization control is 16bits wide*/ >> + lane_reg_size = 0x2; >> + } else if (speed == PCIE_SPEED_16_0GT) { >> + presets = pp->presets.eq_presets_Ngts[EQ_PRESET_TYPE_16GTS]; >> + lane_eq_offset = PCI_PL_16GT_LE_CTRL; >> + cap_id = PCI_EXT_CAP_ID_PL_16GT; >> + lane_reg_size = 0x1; >> + } >> + >> + if (presets[0] == PCI_EQ_RESV) >> + return; >> + >> + cap = dw_pcie_find_ext_capability(pci, cap_id); >> + if (!cap) >> + return; >> + >> + /* >> + * Write preset values to the registers byte-by-byte for the given >> + * number of lanes and register size. >> + */ >> + for (i = 0; i < pci->num_lanes * lane_reg_size; i++) >> + dw_pcie_writeb_dbi(pci, cap + lane_eq_offset + i, presets[i]); >> +} >> + >> +static void dw_pcie_config_presets(struct dw_pcie_rp *pp) >> +{ >> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); >> + enum pci_bus_speed speed = pcie_link_speed[pci->max_link_speed]; >> + > > Please add a comment stating that the equalization needs to be performed at all > lower data rates for each lane. > >> + if (speed >= PCIE_SPEED_8_0GT) >> + dw_pcie_program_presets(pp, PCIE_SPEED_8_0GT); >> + >> + if (speed >= PCIE_SPEED_16_0GT) >> + dw_pcie_program_presets(pp, PCIE_SPEED_16_0GT); > > I think we need to check 'Link Equalization Request' before performing > equalization? This will also help us to warn users if they didn't specify the > property in DT if hardware expects equalization. > Ok I will add a check in dw_pcie_program_presets() if there is no dt property for a particular data rate/speed in next patch. - Krishna Chaitanya. > Currently, even if DT specifies equalization presets for 32GT/s, driver is not > making use of them. > - Mani >