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Signed-off-by: Marcelo Schmitt --- Change log v3 -> v4: - Minor adjust to AD4134 IIO Doc that made the doc 1 line shorter. Documentation/iio/ad4134.rst | 127 +++++++++++++++++++++++++++++++++++ Documentation/iio/index.rst | 1 + MAINTAINERS | 1 + 3 files changed, 129 insertions(+) create mode 100644 Documentation/iio/ad4134.rst diff --git a/Documentation/iio/ad4134.rst b/Documentation/iio/ad4134.rst new file mode 100644 index 000000000000..c0889a21cd77 --- /dev/null +++ b/Documentation/iio/ad4134.rst @@ -0,0 +1,127 @@ +.. SPDX-License-Identifier: GPL-2.0-only + +============= +AD4134 driver +============= + +Device driver for Analog Devices Inc. AD4134 and similar ADCs. + +Supported devices +================= + +* `AD4134 `_ +* `AD7134 `_ + +Wiring connections +------------------ + +AD4134 and similar ADCs can operate in a few different wiring configurations. +Because AD4134 also supports control modes other than through SPI protocol, +the following pins must be statically set for all of the wiring modes described +below. + ++----------------------------+----------------------+--------------------+ +| Pin Function | Level | Description | ++============================+======================+====================+ +| PIN/SPI | High | SPI control mode | ++----------------------------+----------------------+--------------------+ +| MODE | Low | ASRC slave mode | ++----------------------------+----------------------+--------------------+ +| DEC0/DCLKI | Low | DCLK input | ++----------------------------+----------------------+--------------------+ +| DEC1/DCLKMODE | Low | Gated DCLK | ++----------------------------+----------------------+--------------------+ + +Minimum I/O mode +^^^^^^^^^^^^^^^^ + +The minimum I/O mode wiring allows AD4134 register and data access with the +conventional set of SPI bus lines. In this mode, the peripheral CS pin must be +tied to GND. A possible connection schema that sets AD4134 digital interface for +minimum I/O mode is:: + + +------------+ +-------------+ + | AD4134 | | SPI | + | | | Controller | + | DCLK |<--+ | | + | SCLK |<--+---- | SCLK | + | SDI |<--------| SDO | + | SDO |-------->| SDI | + | ODR |<--------| GPIO | + | CS |----+ | | + +------------+ | +-------------+ + V + GND + +Set ``adi,spi-mode = "no-cs"`` in device tree to indicate the device is +connected in minimum I/O wiring configuration. + +SPI 4-wire mode - single lane +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The conventional SPI 4-wire configuration except a multiplexer is used to +select between SDO (for register data) and DOUT0 (for ADC sample data).:: + + +-----------------------+ +-----------------+ + | AD4134 | | SPI Controller | + | | | | + | SPI interface SCLK |<------------------------| SCLK | + | for register CS |<------------------------| CS | + | access SDI |<------------------------| SDO | + | SDO |------->|¯¯¯¯\ | | + | | |MUX >--------->| SDI | + | Data interface DOUT0 |------->|____/ | | + | for ADC sample | ^ | | + | data read | | | | + | DCLK |<------------------------| DCLK | + | ODR |<----------------+ +->| Offload Trigger | + +-----------------------+ | | | +-----------------+ + | | +--| PWM1 | + | +-------| PWM0 | + +--------------| GPIO | + +-----------------+ + +Set ``adi,spi-mode = "4-wire"`` in device tree to indicate the device is +connected in SPI 4-wire configuration. + +For SPI offload operation, a PWM is connected to the ADC ODR pin. The ``pwms`` +firmware property specifies the PWM that is connected to the ADC. The SPI +offload will have a ``trigger-sources`` property to indicate the SPI offload +(PWM) trigger source. + +To achieve high sample rates while meeting ADC timing requirements, an offset +must be added between the rising edges of PWM0 and PWM1 to delay the SPI +transfer until ADC sample data is available. This requires a specialized PWM +controller that can provide such an offset. The `AD4134-FMC HDL project`_, for +example, can be configured to sample AD4134 at high speed sample rates. + +.. _AD4134-FMC HDL project: https://analogdevicesinc.github.io/hdl/projects/ad4134_fmc/index.html + +SPI 4-wire mode - multi-lane +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Maximum throughput rate can be achieved by reading 4 input lines simultaneously.:: + + +-----------------------+ +-----------------+ + | AD4134 | | SPI Controller | + | | | | + | SPI interface SCLK |<------------------------| SCLK | + | for register CS |<------------------------| CS | + | access SDI |<------------------------| SDO | + | SDO |------->|¯¯¯¯\ | | + | | |MUX >--------->| SDI0 | + | Data interface DOUT0 |------->|____/ | | + | for ADC sample | ^ | | + | data read DOUT1 |------------------------>| SDI1 | + | DOUT2 |------------------------>| SDI2 | + | DOUT3 |------------------------>| SDI3 | + | DCLK |<------------------------| DCLK | + | ODR |<----------------+ +->| Offload Trigger | + +-----------------------+ | | | +-----------------+ + | | +--| PWM1 | + | +-------| PWM0 | + +--------------| GPIO | + +-----------------+ + +Each of SDI0 to SDI3 connect to a different SPI controller deserializer +(``spi-rx-bus-width = <1>, <1>, <1>, <1>``). diff --git a/Documentation/iio/index.rst b/Documentation/iio/index.rst index d0fb32f4b80f..3a49e08a2366 100644 --- a/Documentation/iio/index.rst +++ b/Documentation/iio/index.rst @@ -23,6 +23,7 @@ Industrial I/O Kernel Drivers ad4000 ad4030 ad4062 + ad4134 ad4691 ad4695 ad7191 diff --git a/MAINTAINERS b/MAINTAINERS index 3a2dfd1a4fd8..82a810ac788e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1533,6 +1533,7 @@ L: linux-iio@vger.kernel.org S: Supported W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml +F: Documentation/iio/ad4134.rst F: drivers/iio/adc/ad4134.c ANALOG DEVICES INC AD4170-4 DRIVER -- 2.53.0