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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3a851630206sm9675364a91.0.2026.10.07.04.35.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 07 Oct 2026 04:35:55 -0700 (PDT) Message-ID: Date: Wed, 7 Oct 2026 17:05:45 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/5] arm64: dts: qcom: glymur: Add UFS nodes To: Pradeep Pragallapati , Dmitry Baryshkov Cc: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Avri Altman , Bart Van Assche , Bjorn Andersson , Konrad Dybcio , gopikrishna.garmidi@oss.qualcomm.com, jagadeesh.kona@oss.qualcomm.com, Abel Vesa , Abel Vesa , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, nitin.rawat@oss.qualcomm.com, sibi.sankar@oss.qualcomm.com, Taniya Das References: <20261007-glymur_ufs_qcb_enablement-v3-0-84cf4f861415@oss.qualcomm.com> <20261007-glymur_ufs_qcb_enablement-v3-3-84cf4f861415@oss.qualcomm.com> <297690cb-64d8-4e7d-9d97-66680f6a2b99@oss.qualcomm.com> Content-Language: en-US From: Pankaj Patil In-Reply-To: <297690cb-64d8-4e7d-9d97-66680f6a2b99@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: DVQxVt2BTBe-5X_sd_TYbxbgZU5qaTWy X-Authority-Analysis: v=2.4 cv=aKFlOr9m c=1 sm=1 tr=0 ts=6ac62e9e cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=P-IC7800AAAA:8 a=EUspDBNiAAAA:8 a=1LCiuseMYk0cAX_2M9wA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 a=d3PnA9EDa4IxuAV0gXij:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDA3MDA0NiBTYWx0ZWRfXxQ9WbUJ0iJZU 4q0+TewtTA7feHfj2KmeU+h6LEhlrvzBALf5aZTDrh6mlZ5FzjjhE+idbOFUgV5/ouo2ZOvqf2d DFkLXX8wKIne4aF3VyTybF3+Hq6Qrzk= X-Proofpoint-ORIG-GUID: DVQxVt2BTBe-5X_sd_TYbxbgZU5qaTWy X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDA3MDA0NiBTYWx0ZWRfXwj2f8JiFUOwa R7D7j+lfVA2Re+yfAmz39f9xHu0W12Gi/h07X3e4SflbLHOGgR1slNhIgcE78XVabotO3pBDREN MSUrQZJBUZ3vfLEEi//p00+yK4rm4Wk5cSzC0TPA7VO/65Q5p8xle2yOIVMMlCZl/pyix7veU3A UgmOtF/HI2dq5d1rJgckMaN7YXe0812kfs7d5m+HEleSQ8msb2yI9yyslUxsLxL1zcTtXSDFzES +nbs31HAmvYYc1dbdUrZNPOn1NL14aa3OJs4KUyxeTExGZwFswuUse/UFKXmqQyur/1Q3LCdWCV 38hBHfU2yArjgyPFXG+JirHYRs8aWCaHLooAee2uoCcRSIhnFrqJ/nhhMSvnTKFri7bHhZ8ozi8 60ctshESKUWqC2+qZTzJVfapbS4UGdEvQaKmVJKVMCZwNGyN1CQB42tOmrSDVAUlnrpy7I246V+ 0Ypqeq/KpCGO8xmNQnw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-07_04,2026-10-06_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 bulkscore=0 adultscore=0 lowpriorityscore=0 spamscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2610070046 On 10/7/2026 4:30 PM, Pradeep Pragallapati wrote: > > > On 10/7/2026 1:13 PM, Dmitry Baryshkov wrote: >> On Wed, Oct 07, 2026 at 11:59:36AM +0530, Pradeep P V K wrote: >>> Add UFS PHY and UFS host controller nodes for Glymur SoC. >>> >>> Reviewed-by: Abel Vesa >>> Signed-off-by: Pradeep P V K >>> --- >>> arch/arm64/boot/dts/qcom/glymur.dtsi | 125 ++++++++++++++++++++++++++++++++++- >>> 1 file changed, 122 insertions(+), 3 deletions(-) >>> >>> @@ -4102,6 +4102,125 @@ rng: rng@10c3000 { >>> reg = <0x0 0x010c3000 0x0 0x1000>; >>> }; >>> >>> + ufs_mem_phy: phy@1d80000 { >>> + compatible = "qcom,glymur-qmp-ufs-phy"; >>> + reg = <0x0 0x01d80000 0x0 0x2000>; >>> + >>> + clocks = <&rpmhcc RPMH_CXO_CLK>, >>> + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, >>> + /* UFS and PCIE4 share the same clkref */ >>> + <&tcsr TCSR_PCIE_4_CLKREF_EN>; >>> + >>> + clock-names = "ref", >>> + "ref_aux", >>> + "qref"; >>> + >>> + resets = <&ufs_mem_hc 0>; >>> + reset-names = "ufsphy"; >> >> power-domains = <&gcc GCC_UFS_PHY_GDSC> ? Or is there >> GCC_UFS_MEM_PHY_GDSC, which is simply not described in gcc? >> >> If there are none, it should be reflected in the DT bindings, together >> with the explanation in the commit message. >> > Yes, Glymur SoC does not support UFS PHY GDSC. Sure, i will update the DT-bindings accordingly and include the explanation in the commit of next patch series. The support exists? I can see the gdsc in gcc-glymur.c https://elixir.bootlin.com/linux/v7.3-rc5/source/drivers/clk/qcom/gcc-glymur.c#L7768 > >>> + >>> + #clock-cells = <1>; >>> + #phy-cells = <0>; >>> + >>> + status = "disabled"; >>> + }; >>> + >> > >