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([2a01:e0a:106d:1080:9e08:19eb:ca8a:9b73]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48dfd5128f1sm4861952f8f.59.2026.10.16.05.34.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 16 Oct 2026 05:34:05 -0700 (PDT) Message-ID: Date: Fri, 16 Oct 2026 14:34:04 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Neil Armstrong Reply-To: Neil Armstrong Subject: Re: [PATCH] PCI: qcom: Advertise hotplug with no command completion support To: Krishna Chaitanya Chundru , Manivannan Sadhasivam , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260314-hotplug-v1-1-96ac87d93867@oss.qualcomm.com> <1ae8d4f0-1c32-4dbd-a18e-7a2ce2627efc@oss.qualcomm.com> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: <1ae8d4f0-1c32-4dbd-a18e-7a2ce2627efc@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Hi, On 10/16/26 13:08, Krishna Chaitanya Chundru wrote: > > > On 10/16/2026 3:54 PM, Neil Armstrong wrote: >> Hi, >> >> On 3/14/26 02:56, Krishna Chaitanya Chundru wrote: >>> QCOM PCIe controller advertise hotplug capability in hardware but do not >>> support hotplug command completion. As a result, the PCI core registers >>> the pciehp service and issues hotplug commands that never gets completions, >>> leading to repeated timeout warnings and multi-second delays during boot >>> and suspend/resume. >>> >>> Commit a54db86ddc153 ("PCI: qcom: Do not advertise hotplug capability for >>> IPs v2.7.0 and v1.9.0") avoided these timeouts by clearing the Hot-Plug >>> Capability bit entirely, which also disabled all hotplug functionality. >>> >>> Instead of disabling hotplug, mark these controllers as not supporting >>> command completion by setting the No Command Completed Support (NCCS) bit >>> in the Slot Capabilities register. This prevents the PCI hotplug driver >>> from waiting for commands completion while still allowing hotplug-related >>> functionality such as Data Link Layer state change events. >> >> I'm a little late to the party, but marking the RC as Hotplus means the bridge >> is marked as is_pciehp and pci_bridge_d3_possible() returns false. >> >> This means this breaks D3Cold support completely since in >> __pci_host_common_d3cold_possible() >> we now check all PCI devices, including bridges, and the RC is not set in >> D3Hot anymore. >> >> The only way to enable D3Cold is to pass pcie_port_pm=force to allow D3 on all >> Hotplug bridges. Which may be wrong on TB bridges. >> > Hi Neil, > can you enable hotplug driver and use this patch [1], that should solve the issue. > > [1] > https://patch.msgid.link/20260729165005.896725-1-manivannan.sadhasivam@oss.qualcomm.com Thanks this fixes the issue, Neil > >> Neil >> >>> >>> Signed-off-by: Krishna Chaitanya Chundru >>> --- >>>   drivers/pci/controller/dwc/pcie-qcom.c | 2 +- >>>   1 file changed, 1 insertion(+), 1 deletion(-) >>> >>> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c >>> b/drivers/pci/controller/dwc/pcie-qcom.c >>> index >>> 67a16af69ddc75fca1b123e70715e692a91a9135..a2924610f3625f2456a491473c135840e31bafb9 >>> 100644 >>> --- a/drivers/pci/controller/dwc/pcie-qcom.c >>> +++ b/drivers/pci/controller/dwc/pcie-qcom.c >>> @@ -358,7 +358,7 @@ static void qcom_pcie_clear_hpc(struct dw_pcie *pci) >>>       dw_pcie_dbi_ro_wr_en(pci); >>>         val = readl(pci->dbi_base + offset + PCI_EXP_SLTCAP); >>> -    val &= ~PCI_EXP_SLTCAP_HPC; >>> +    val |= PCI_EXP_SLTCAP_NCCS; >>>       writel(val, pci->dbi_base + offset + PCI_EXP_SLTCAP); >>>         dw_pcie_dbi_ro_wr_dis(pci); >>> >>> --- >>> base-commit: 0257f64bdac7fdca30fa3cae0df8b9ecbec7733a >>> change-id: 20260313-hotplug-4c296595b5b8 >>> >>> Best regards, >> >