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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-615a8f2d554sm10031187a12.27.2025.08.06.05.56.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 06 Aug 2025 05:56:44 -0700 (PDT) Message-ID: Date: Wed, 6 Aug 2025 14:56:43 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1] ufs: ufs-qcom: Align programming sequence of Shared ICE for UFS controller v5 To: Manivannan Sadhasivam , Palash Kambar Cc: James.Bottomley@hansenpartnership.com, martin.petersen@oracle.com, linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org, linux-kernel@vger.kernel.org, quic_nitirawa@quicinc.com References: <20250806063409.21206-1-quic_pkambar@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: iyLcevKr9dU_JdNgWcq8OsR6DKEEUzwl X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODA2MDAwOCBTYWx0ZWRfX2nG5kQjUGw+h RkEfFneps0Gy/VhUGf84lsrwZr2QQA0gYERowRwYEVJXb3Or6GgffYiKDuz3wZRDMIEO9POVhmG y74+tU19DpXd5fVw5rGO3xckp+dFmqZcHxr2IrW4ae2ERfn2CjpLNKQfNvc9w+N1i3kC+xxWtwW cbs0D4nXcy+jj2badRjeWV9PyokFKbTpgaj6hYVWYl9EvlWwIKiqa8cjZfEJOsdsE//IFtoepax zlgjrXn2wTl4Kwggb2ciE2nCvER09tTzpaGov5XzMYiFW/uQ+mzq69hjFEXF4OiKaYjR7gjmPGs b9qWxvIgnbPX3kyYbSTz29ruGgo0Bd20fpZTYUeMmvfIGcoMGJK1JBSY0mHXSs+f0yo2JEon/qO L/67sxHo X-Authority-Analysis: v=2.4 cv=JIo7s9Kb c=1 sm=1 tr=0 ts=6893510f cx=c_pps a=oc9J++0uMp73DTRD5QyR2A==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=COk6AnOGAAAA:8 a=CykVZ_nljMR9ycAI1QEA:9 a=QEXdDO2ut3YA:10 a=iYH6xdkBrDN1Jqds4HTS:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: iyLcevKr9dU_JdNgWcq8OsR6DKEEUzwl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-06_03,2025-08-06_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 clxscore=1015 impostorscore=0 suspectscore=0 bulkscore=0 malwarescore=0 phishscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508060008 On 8/6/25 1:14 PM, Manivannan Sadhasivam wrote: > On Wed, Aug 06, 2025 at 12:04:09PM GMT, Palash Kambar wrote: >> Disable of AES core in Shared ICE is not supported during power >> collapse for UFS Host Controller V5.0. >> >> Hence follow below steps to reset the ICE upon exiting power collapse >> and align with Hw programming guide. >> >> a. Write 0x18 to UFS_MEM_ICE_CFG >> b. Write 0x0 to UFS_MEM_ICE_CFG >> >> Signed-off-by: Palash Kambar >> --- [...] > >> + ufshcd_readl(hba, UFS_MEM_ICE); >> + ufshcd_writel(hba, 0x0, UFS_MEM_ICE); >> + ufshcd_readl(hba, UFS_MEM_ICE); > > Why do you need readl()? Writes to device memory won't get reordered. I'm not sure if we need a delay between them, otherwise they'll happen within a couple cycles of each other which may not be enough since this is a synchronous reset and the clock period is 20-50ns when running at XO (19.2 / 38.4 MHz) rate Konrad