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Mon, 15 Jun 2026 10:24:32 -0700 (PDT) X-Received: by 2002:a05:6a00:2308:b0:842:5931:7b88 with SMTP id d2e1a72fcca58-8434caec171mr16906404b3a.1.1781544272268; Mon, 15 Jun 2026 10:24:32 -0700 (PDT) Received: from [192.168.1.48] ([122.164.85.44]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8434accdca8sm13328459b3a.18.2026.06.15.10.24.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 15 Jun 2026 10:24:31 -0700 (PDT) Message-ID: Date: Mon, 15 Jun 2026 22:54:26 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/3] regulator: qcom-refgen: add support for the IPQ9650 SoC To: Mark Brown Cc: Liam Girdwood , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Dmitry Baryshkov References: <20260615-ipq9650_refgen-v3-0-5f611623629c@oss.qualcomm.com> <20260615-ipq9650_refgen-v3-3-5f611623629c@oss.qualcomm.com> <737655dd-2059-421d-a9ca-91ebd1b1209b@sirena.org.uk> Content-Language: en-US From: Kathiravan Thirumoorthy In-Reply-To: <737655dd-2059-421d-a9ca-91ebd1b1209b@sirena.org.uk> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjE1MDE4NCBTYWx0ZWRfXxv3lpqu3aPys 6HW8Lx7qbyxQPxrZ1GvvL8LWEG14Z0JWuSRweVgXRPyOzyFjQbTMES5+pwtZokyRp11OBhZl9sl A/NtOuC80Ori3PRQxUiUZiW46OVq65h77lkab71mf/xPrAHmmyrxPBgOH3aODZ7aeYK3wr9cT8/ s0z0uH3BKC/Q1+ps06jePXc07S+wtFPIeSyFnfy1xsOOps0i9dJ/Vt/Hy2+1DkbNRqueoJkTvFt GIWfO5hVT6OkIVsXpRp6MfTlzDd9kcL4/gET/sqfUgfsUjlKcoOfAqRykXAA4jlKfKXqg9HLD99 OzHvZSYYuCpkmch7LR4/or2lwgRAC7MV6oLTND2swmjHXCHIeJ3ZmRN5S2WBHRuj9baVo8xMtBp ZFBE1bHYGBNLjc6x4WIP12E21SFrraZs5VfBuVQog0sFIZrARgaEGyIiQsfDUnmVm01UYg8+2NS dvvnlMF0V3P6QoY7ljA== X-Proofpoint-ORIG-GUID: Mj8WrEwRKwiZeYmPYaCfe3euvnUp2-UQ X-Proofpoint-GUID: Mj8WrEwRKwiZeYmPYaCfe3euvnUp2-UQ X-Proofpoint-Spam-Info: AW1haW4tMjYwNjE1MDE4NCBTYWx0ZWRfXwf5JexN1yFyY +5cpuTDcye5m7jXaQAmJ+qQpMTODobQapKZq+E1HEBhRRGngHRtoMgL96S9X5zFh58B7D5X+RpK IMif9f6q7jRl7Epgw5GLrgx9NNH9O/c= X-Authority-Analysis: v=2.4 cv=MsRiLWae c=1 sm=1 tr=0 ts=6a303551 cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=BchUXt3FRQcObq55vMoYrw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=7WPBTj7QaewYWrzPdxoA:9 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-15_04,2026-06-15_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 adultscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606040000 definitions=main-2606150184 On 6/15/2026 9:28 PM, Mark Brown wrote: > On Mon, Jun 15, 2026 at 02:05:49PM +0530, Kathiravan Thirumoorthy wrote: >> IPQ9650 SoC has 2 REFGEN blocks providing the reference current to the >> PCIe and USB, UNIPHY PHYs. For the other SoCs, clock for this block is >> enabled on power up but that's not the case for IPQ9650 and we have to >> enable those clocks explicitly to bring up the PHYs properly. >> +static int qcom_ipq9650_refgen_enable(struct regulator_dev *rdev) >> +{ >> + struct qcom_refgen_drvdata *drvdata = rdev_get_drvdata(rdev); >> + int ret; >> + >> + ret = clk_bulk_prepare_enable(drvdata->num_clks, drvdata->clks); >> + if (ret) >> + return ret; >> + >> + return 0; >> +} >> +static int qcom_ipq9650_refgen_disable(struct regulator_dev *rdev) >> +{ >> + struct qcom_refgen_drvdata *drvdata = rdev_get_drvdata(rdev); >> + >> + clk_bulk_disable_unprepare(drvdata->num_clks, drvdata->clks); >> + >> + return 0; >> +} >> +static const struct regulator_desc ipq9650_refgen_desc = { >> + .enable_reg = REFGEN_REG_REFGEN_STATUS, >> + .enable_mask = REFGEN_STATUS_OUT_MASK, >> + .enable_val = REFGEN_STATUS_OUT_ENABLE, >> + .ops = &(const struct regulator_ops) { >> + .enable = qcom_ipq9650_refgen_enable, >> + .disable = qcom_ipq9650_refgen_disable, >> + .is_enabled = regulator_is_enabled_regmap, >> + }, > This looks like a get_status() operation, not an enable operation? The > enables and disables are pure clock operations. Thanks, Mark for the review. If I understand correctly, I should track the clock enable/disable operations and return that state in the is_enabled() callback (as I did in v1). Please let me know if my understanding does not align with your expectations.