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Sampat" To: , , CC: , , , , , , , , , , , Subject: [Patch v4 3/4] x86/sev: Add guest support for Enhanced SMT Protection Date: Mon, 9 Nov 2026 20:35:13 +0000 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000D894D:EE_|PH0PR12MB7469:EE_ X-MS-Office365-Filtering-Correlation-Id: 039191fe-fb97-4bd7-64f3-08df3ea11534 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|23010399003|82310400026|1800799024|36860700016|11063799006|261022105027099003|261026140227099003|261021121427099003|56012099006|261021123027099003|261028144727099003|261009223027099003|261102123227099003|10067099003|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: GWjR03fc6EqM4rFw9zJhTnDWzzQevPcrf4CIImzAyKSl1w0X/71oEarvFk96ir9/6wVOJGvkf7VnEDP5tvDw2EnpWRB365ep8ygPpMZk2HTnQ5BebwvbLdsFZDVtZ45cmwIkMwl28GvYcnwCZTPTQPMTLRFB/C+VAHF5RoT81gy4P+uzLyUm/hMLiRJ3c383Tomb9XX2Daq7NpevWB7UmBqWDnvz2CjM3jYvvd5l+fEsOq3HYFN4YZEXwKKassMTPOghcwXGT5y/EWf/SlWomc/1lehk7i0dBnKagK9wh5SyYIjtiTSGxyK9WvcekHaC3IMnBu0aZJspEOki8sLLSpCyZ6r+51LWEJDJXKdJ5x0/3pkld70xHVuRblTJU0mGyCFf087F4AxuffdG9WywnIZqKtmgvMhhLSxbZYOJ+QFWrzt8YYtNVV41ovn4mwD4C1KaoKN1xPzNslWCG9NP7Al2ExWRamH/RVlRCvOpikETRs74/CQMRVYp/A5MQlCayz0l2tSykotGKAeD75Ak4OEq3+zY8EMA80ArRMwlgawICGaQ/Lkg/xRXQTLEjVc6Dw1PNIFTm8AT/uSV0lBv5Zaj8SeVVs+qCPF8MSCYHBQRQ/N+bhZF98SPjpj0JpRQ/bJGjy+OwG55xWK++I2NR7xG7D5DnJMeA1nA2rORTyrLBF6KrDt6XAXMWi/TMbu5BE22JuOw/xH6IOQEuJWL1A== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(23010399003)(82310400026)(1800799024)(36860700016)(11063799006)(261022105027099003)(261026140227099003)(261021121427099003)(56012099006)(261021123027099003)(261028144727099003)(261009223027099003)(261102123227099003)(10067099003)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: shgQrhK68z3nU0yWAnNrlKmjZWpjIlNROcbHCcKGcReJQE8lPpM9dOYJsjCHGg7yQonSuymyGVrQ77xWipk/OZKo+MMlen6wGslkkS8E0Hq2XyuXtm5aYfJb/KO1kffDqgLWbFhY15Wf/en/HTG2uiwXkKiOttfyvG/KQ/6D7LEssbTPijpie9YF5dGk26a1KHDSeW3SLBQfD9xcf82mBDzw6hvZm5aYMrI3/2qgK98SwVSQWXSkpUFSREcflKdPz3xwJpQVRVZsxYno/GFFJ06aTnbp38/XHHfkoDN6X5748gLqxw/70NlmdcQCeNqkbQqyNbGpX6OjOnFei8IB7ZG4phlO61ChDRt3QOqmf+0GBipClDYC2mNc/49vR3Z52b6s/PCgm62P3eW9swu9jYRLQfhGH4EF+wxzUIX064/84dKCsEGW781vL5R82+VN X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2026 20:36:07.4965 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 039191fe-fb97-4bd7-64f3-08df3ea11534 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000D894D.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7469 Enhanced SMT Protection requires every VMSA to carry the vCPU's identity and the mask of SMT siblings it may co-run with. The guest builds the VMSA itself when bringing up an AP, so populate both fields there, before the page is turned into a VMSA and while it is still writable. Fully set the sibling mask so that all threads of the same guest trust each other. Reviewed-by: Tom Lendacky Signed-off-by: Pratik R. Sampat --- v3..v4: No Change --- arch/x86/boot/compressed/sev.c | 6 ++++-- arch/x86/coco/sev/core.c | 13 +++++++++++++ arch/x86/include/asm/msr-index.h | 4 +++- 3 files changed, 20 insertions(+), 3 deletions(-) diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c index c6512f2ea31e..4e0fa5a5f70b 100644 --- a/arch/x86/boot/compressed/sev.c +++ b/arch/x86/boot/compressed/sev.c @@ -188,7 +188,8 @@ bool sev_es_check_ghcb_fault(unsigned long address) MSR_AMD64_SNP_RESERVED_BIT13 | \ MSR_AMD64_SNP_RESERVED_BIT15 | \ MSR_AMD64_SNP_SECURE_AVIC | \ - MSR_AMD64_SNP_RESERVED_BITS19_22 | \ + MSR_AMD64_SNP_ESMT_PROT | \ + MSR_AMD64_SNP_RESERVED_BITS20_22 | \ MSR_AMD64_SNP_RESERVED_MASK) #ifdef CONFIG_AMD_SECURE_AVIC @@ -204,7 +205,8 @@ bool sev_es_check_ghcb_fault(unsigned long address) */ #define SNP_FEATURES_IMPL (MSR_AMD64_SNP_DEBUG_SWAP | \ MSR_AMD64_SNP_SECURE_TSC | \ - SNP_FEATURE_SECURE_AVIC) + SNP_FEATURE_SECURE_AVIC | \ + MSR_AMD64_SNP_ESMT_PROT) u64 snp_get_unsupported_features(u64 status) { diff --git a/arch/x86/coco/sev/core.c b/arch/x86/coco/sev/core.c index cc292d7c6fd1..b89766bb9365 100644 --- a/arch/x86/coco/sev/core.c +++ b/arch/x86/coco/sev/core.c @@ -89,6 +89,7 @@ static const char * const sev_status_feat_names[] = { [MSR_AMD64_SNP_VMSA_REG_PROT_BIT] = "VMSARegProt", [MSR_AMD64_SNP_SMT_PROT_BIT] = "SMTProt", [MSR_AMD64_SNP_SECURE_AVIC_BIT] = "SecureAVIC", + [MSR_AMD64_SNP_ESMT_PROT_BIT] = "ESMTProt", [MSR_AMD64_SNP_IBPB_ON_ENTRY_BIT] = "IBPBOnEntry", }; @@ -849,6 +850,18 @@ static int wakeup_cpu_via_vmgexit(u32 apic_id, unsigned long start_ip, unsigned vmsa->vmpl = snp_vmpl; vmsa->sev_features = sev_status >> 2; + if (sev_status & MSR_AMD64_SEV_SNP_ENABLED && + (sev_status & MSR_AMD64_SNP_ESMT_PROT)) { + vmsa->vcpu_id = apic_id; + /* + * The mask fully set puts every vCPU in one group, so any two + * of them may be co-resident. A legal ESMTP sibling must + * also match on ASID, so the sibling of a vCPU in guest mode is + * always either another vCPU of this same guest or idle. + */ + vmsa->vcpu_sibling_mask = U32_MAX; + } + /* Populate AP's TSC scale/offset to get accurate TSC values. */ if (cc_platform_has(CC_ATTR_GUEST_SNP_SECURE_TSC)) { vmsa->tsc_scale = snp_tsc_scale; diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index fbcb3313e946..6fd26151d146 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -745,7 +745,9 @@ #define MSR_AMD64_SNP_SMT_PROT BIT_ULL(MSR_AMD64_SNP_SMT_PROT_BIT) #define MSR_AMD64_SNP_SECURE_AVIC_BIT 18 #define MSR_AMD64_SNP_SECURE_AVIC BIT_ULL(MSR_AMD64_SNP_SECURE_AVIC_BIT) -#define MSR_AMD64_SNP_RESERVED_BITS19_22 GENMASK_ULL(22, 19) +#define MSR_AMD64_SNP_ESMT_PROT_BIT 19 +#define MSR_AMD64_SNP_ESMT_PROT BIT_ULL(MSR_AMD64_SNP_ESMT_PROT_BIT) +#define MSR_AMD64_SNP_RESERVED_BITS20_22 GENMASK_ULL(22, 20) #define MSR_AMD64_SNP_IBPB_ON_ENTRY_BIT 23 #define MSR_AMD64_SNP_IBPB_ON_ENTRY BIT_ULL(MSR_AMD64_SNP_IBPB_ON_ENTRY_BIT) #define MSR_AMD64_SNP_RESV_BIT 24 -- 2.43.0