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Tue, 17 Jul 2018 15:30:08 +0200 Subject: Re: [PATCH 2/2] pinctrl: stm32: add syscfg mask parameter To: Ludovic BARRE , Linus Walleij , Rob Herring CC: Maxime Coquelin , , , References: <1531821387-29845-1-git-send-email-ludovic.Barre@st.com> <1531821387-29845-3-git-send-email-ludovic.Barre@st.com> <4acc415d-f162-67a2-57d6-0a7defda434f@st.com> From: Alexandre Torgue Message-ID: Date: Tue, 17 Jul 2018 15:30:08 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.8.0 MIME-Version: 1.0 In-Reply-To: <4acc415d-f162-67a2-57d6-0a7defda434f@st.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit X-Originating-IP: [10.75.127.51] X-ClientProxiedBy: SFHDAG8NODE3.st.com (10.75.127.24) To SFHDAG3NODE2.st.com (10.75.127.8) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2018-07-17_03:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 07/17/2018 03:11 PM, Ludovic BARRE wrote: > Hi > > add Rob, I forgotten rob's mail. > > On 07/17/2018 11:56 AM, Ludovic Barre wrote: >> From: Ludovic Barre >> >> This patch adds mask parameter to define IRQ mux field. >> This field could vary depend of IRQ mux selection register. >> To avoid backward compatibility, the drivers set >> the legacy value by default. >> >> Signed-off-by: Ludovic Barre Acked-by: Alexandre TORGUE >> --- >>   drivers/pinctrl/stm32/pinctrl-stm32.c | 16 ++++++++++++++-- >>   1 file changed, 14 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c >> b/drivers/pinctrl/stm32/pinctrl-stm32.c >> index dfed609..f756232 100644 >> --- a/drivers/pinctrl/stm32/pinctrl-stm32.c >> +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c >> @@ -46,6 +46,8 @@ >>   #define STM32_GPIO_PINS_PER_BANK 16 >>   #define STM32_GPIO_IRQ_LINE     16 >> +#define SYSCFG_IRQMUX_MASK GENMASK(3, 0) >> + >>   #define gpio_range_to_bank(chip) \ >>           container_of(chip, struct stm32_gpio_bank, range) >> @@ -1033,6 +1035,7 @@ static int stm32_pctrl_dt_setup_irq(struct >> platform_device *pdev, >>       struct device *dev = &pdev->dev; >>       struct regmap *rm; >>       int offset, ret, i; >> +    int mask, mask_width; >>       parent = of_irq_find_parent(np); >>       if (!parent) >> @@ -1052,12 +1055,21 @@ static int stm32_pctrl_dt_setup_irq(struct >> platform_device *pdev, >>       if (ret) >>           return ret; >> +    ret = of_property_read_u32_index(np, "st,syscfg", 2, &mask); >> +    if (ret) >> +        mask = SYSCFG_IRQMUX_MASK; >> + >> +    mask_width = fls(mask); >> + >>       for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) { >>           struct reg_field mux; >>           mux.reg = offset + (i / 4) * 4; >> -        mux.lsb = (i % 4) * 4; >> -        mux.msb = mux.lsb + 3; >> +        mux.lsb = (i % 4) * mask_width; >> +        mux.msb = mux.lsb + mask_width - 1; >> + >> +        dev_dbg(dev, "irqmux%d: reg:%#x, lsb:%d, msb:%d\n", >> +            i, mux.reg, mux.lsb, mux.msb); >>           pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux); >>           if (IS_ERR(pctl->irqmux[i])) >>