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([2a01:e0a:3d9:2080:fb2e:6266:4e39:ce68]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-447f73d4a3csm20944195e9.22.2025.05.20.00.56.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 20 May 2025 00:56:08 -0700 (PDT) Message-ID: Date: Tue, 20 May 2025 09:56:07 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: neil.armstrong@linaro.org Reply-To: Neil Armstrong Subject: Re: [PATCH v4 10/30] drm/msm/dpu: get rid of DPU_CTL_FETCH_ACTIVE To: Dmitry Baryshkov , Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Vinod Koul , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov References: <20250519-dpu-drop-features-v4-0-6c5e88e31383@oss.qualcomm.com> <20250519-dpu-drop-features-v4-10-6c5e88e31383@oss.qualcomm.com> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 19/05/2025 18:04, Dmitry Baryshkov wrote: > From: Dmitry Baryshkov > > Continue migration to the MDSS-revision based checks and replace > DPU_CTL_FETCH_ACTIVE feature bit with the core_major_ver >= 7 check. > > Signed-off-by: Dmitry Baryshkov > Reviewed-by: Abhinav Kumar > Signed-off-by: Dmitry Baryshkov > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +-- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 -- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 2 +- > 3 files changed, 2 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > index 0863e5cfb3283ed32f61ddd4483220742df8633d..6fed2cce082c476c1f7f8ee683f2a6f3eeaa5231 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > @@ -105,8 +105,7 @@ > (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC)) > > #define CTL_SC7280_MASK \ > - (BIT(DPU_CTL_FETCH_ACTIVE) | \ > - BIT(DPU_CTL_VM_CFG) | \ > + (BIT(DPU_CTL_VM_CFG) | \ > BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH)) > > #define INTF_SC7180_MASK \ > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > index 9981d090b689b46bbc378d1965b0efd1df0efa8b..82f04de6300eca7d05ece3ac880c26f3a56505b9 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > @@ -132,14 +132,12 @@ enum { > /** > * CTL sub-blocks > * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display > - * @DPU_CTL_FETCH_ACTIVE: Active CTL for fetch HW (SSPPs) > * @DPU_CTL_VM_CFG: CTL config to support multiple VMs > * @DPU_CTL_DSPP_BLOCK_FLUSH: CTL config to support dspp sub-block flush > * @DPU_CTL_MAX > */ > enum { > DPU_CTL_SPLIT_DISPLAY = 0x1, > - DPU_CTL_FETCH_ACTIVE, > DPU_CTL_VM_CFG, > DPU_CTL_DSPP_SUB_BLOCK_FLUSH, > DPU_CTL_MAX > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > index 2dfb7db371a3915f663cf134e4dd62f92224185b..772df53bfc4fcc2ff976f66ef7339be1ae3da8f4 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > @@ -809,7 +809,7 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev, > else > c->ops.update_pending_flush_dspp = dpu_hw_ctl_update_pending_flush_dspp; > > - if (c->caps->features & BIT(DPU_CTL_FETCH_ACTIVE)) > + if (mdss_ver->core_major_ver >= 7) > c->ops.set_active_fetch_pipes = dpu_hw_ctl_set_active_fetch_pipes; > > c->idx = cfg->id; > Reviewed-by: Neil Armstrong