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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ace6e41bc41sm104938866b.24.2025.04.25.02.05.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 25 Apr 2025 02:05:17 -0700 (PDT) Message-ID: Date: Fri, 25 Apr 2025 11:05:15 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 1/5] drm/msm/adreno: Implement SMEM-based speed bin To: Akhil P Oommen Cc: Rob Clark , Sean Paul , Abhinav Kumar , Dmitry Baryshkov , David Airlie , Daniel Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <20240709-topic-smem_speedbin-v5-0-e2146be0c96f@linaro.org> <20240709-topic-smem_speedbin-v5-1-e2146be0c96f@linaro.org> <20240715200419.l47ng6efa25in6sg@hu-akhilpo-hyd.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20240715200419.l47ng6efa25in6sg@hu-akhilpo-hyd.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: ULNr4CZ8xZpoKDnCWiWXDx6WuDDf3Uk_ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDI1MDA2NSBTYWx0ZWRfXyrLy3KI12znD jrcXfpqRBug8EFd2nAvWiVFwrj+tEdSKmg70B5RDCtxwlKevCLciBOwZOa1ctTiwFP4+3gtslZW yo03kmXujCwLMVc4kpfuxbCY3G1ZOvUQdViWUDfdfa9BfAzHyhXeEXZ4wFPAjVO/ScnhGbcT9tc uTey0cpKZ4I6TFetO2Qu9xoA7Oz88W0y5Joveq8rqtykb2OU3NpiS+tqBcd5oR084Y5qWTJZvsV zmHEELw2+9JybNksHLIj1RXKe0cXYwLdhCqFpFQ4UDNucjLuOYS5B5NF59PISbdrB22DPucj2t0 p+wYuUj1n4dZAskI0D9Oym5LWWvXxw8+PUw4xXWBaJunz6s6jrToHRVC7LwPNn0IWnRzQp8qvLE NNPRTDGg4g4HCMSyBfOWhxQ3FPH80sW6Pv3BRsTsyEPIYFLnEuL4LJYtbfSby67AUxKpouo3 X-Authority-Analysis: v=2.4 cv=ELgG00ZC c=1 sm=1 tr=0 ts=680b504f cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=KKAkSRfTAAAA:8 a=RALOh4QmxscuBpg08HYA:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: ULNr4CZ8xZpoKDnCWiWXDx6WuDDf3Uk_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-04-25_02,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 malwarescore=0 clxscore=1015 bulkscore=0 phishscore=0 spamscore=0 mlxscore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 mlxlogscore=874 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504250065 On 7/15/24 10:04 PM, Akhil P Oommen wrote: > On Tue, Jul 09, 2024 at 12:45:29PM +0200, Konrad Dybcio wrote: >> On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is >> abstracted through SMEM, instead of being directly available in a fuse. >> >> Add support for SMEM-based speed binning, which includes getting >> "feature code" and "product code" from said source and parsing them >> to form something that lets us match OPPs against. >> >> Due to the product code being ignored in the context of Adreno on >> production parts (as of SM8650), hardcode it to SOCINFO_PC_UNKNOWN. >> >> Signed-off-by: Konrad Dybcio >> --- [...] >> >> int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, >> @@ -1102,9 +1136,9 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, >> devm_pm_opp_set_clkname(dev, "core"); >> } >> >> - if (adreno_read_speedbin(dev, &speedbin) || !speedbin) >> + if (adreno_read_speedbin(adreno_gpu, dev, &speedbin) || !speedbin) >> speedbin = 0xffff; >> - adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin); >> + adreno_gpu->speedbin = speedbin; > > There are some chipsets which uses both Speedbin and Socinfo data for > SKU detection [1]. We don't need to worry about that logic for now. But > I am worried about mixing Speedbin and SKU_ID in the UABI with this patch. > It will be difficult when we have to expose both to userspace. > > I think we can use a separate bitfield to expose FCODE/PCODE. Currently, > the lower 32 bit is reserved for chipid and 33-48 is reserved for speedbin, > so I think we can use the rest of the 16 bits for SKU_ID. And within that > 16bits, 12 bits should be sufficient for FCODE and the rest 8 bits > reserved for future PCODE. So I revisited this patchset and had another thought - maybe we could just extend the speedbin bitfield to cover [63:32] and worry about filling these higher bits in the future, when adding the platforms you mentioned? Do we still have plans to use *both* SMEM and fuse encoding on them? Konrad