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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9e564c6150sm551280266b.81.2024.11.04.06.06.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 04 Nov 2024 06:06:32 -0800 (PST) Message-ID: Date: Mon, 4 Nov 2024 15:06:29 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 2/3] arm64: dts: qcom: x1e80100: Describe TLMM pins for SDC2 To: Abel Vesa , Konrad Dybcio Cc: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Johan Hovold , Dmitry Baryshkov , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org References: <20241022-x1e80100-qcp-sdhc-v3-0-46c401e32cbf@linaro.org> <20241022-x1e80100-qcp-sdhc-v3-2-46c401e32cbf@linaro.org> <327507d8-2dc7-4645-ac3d-d68ff31a84dd@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: ucH2bMspLOMrbT5EHmbG02SU_JOE4N3d X-Proofpoint-GUID: ucH2bMspLOMrbT5EHmbG02SU_JOE4N3d X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 mlxscore=0 impostorscore=0 lowpriorityscore=0 bulkscore=0 suspectscore=0 adultscore=0 clxscore=1015 phishscore=0 malwarescore=0 mlxlogscore=989 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411040123 On 1.11.2024 12:21 PM, Abel Vesa wrote: > On 24-10-28 14:10:54, Konrad Dybcio wrote: >> On 28.10.2024 9:48 AM, Abel Vesa wrote: >>> On 24-10-25 20:34:19, Konrad Dybcio wrote: >>>> On 22.10.2024 12:46 PM, Abel Vesa wrote: >>>>> Describe the SDC2 default and sleep state pins configuration >>>>> in TLMM. Do this in SoC dtsi file since they will be shared >>>>> across multiple boards. >>>>> >>>>> Signed-off-by: Abel Vesa >>>>> --- >>>> >>>> Not very useful on its own but okay.. >>> >>> Fair enough. For some reason, I'm not able to get sdc4 pinconf >>> to work. >> >> Any chance you tried to define 'sdc4_cmd' etc.? This one seems to have >> sdc4 pins on gpio127..=132 > > Yes. > > But since the sdc4 pins can have other functions and since there is no > device that uses them (yet). Shouldn't we just skip describing the sdc4 > pinconf entirely as that should be done on a per-board basis? By that argument, why describe the controller in the first place :| The possible pins are predefined and physically wired up inside the soc Konrad