From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752991AbdK3C2N (ORCPT ); Wed, 29 Nov 2017 21:28:13 -0500 Received: from regular1.263xmail.com ([211.150.99.134]:52310 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752311AbdK3C2L (ORCPT ); Wed, 29 Nov 2017 21:28:11 -0500 X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-RL-SENDER: zyw@rock-chips.com X-FST-TO: enric.balletbo@collabora.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: zyw@rock-chips.com X-UNIQUE-TAG: <397a6dc79b05dfa9921d9bdbab93288e> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Subject: Re: [PATCH 0/4] Move DP phy switch to PHY driver To: Doug Anderson Cc: dri-devel@lists.freedesktop.org, Kishon Vijay Abraham I , Rob Herring , "open list:ARM/Rockchip SoC..." , LKML , Guenter Roeck , Sean Paul , William wu , Rob Herring , David Airlie , Shawn Lin , Catalin Marinas , Elaine Zhang , David Wu , Heiko Stuebner , Kever Yang , Brian Norris , Tomasz Figa , Will Deacon , devicetree@vger.kernel.org, Linux ARM , Jianqun Xu , Caesar Wang , Mark Rutland , Enric Balletbo i Serra References: <1486712654-15431-1-git-send-email-zyw@rock-chips.com> From: Chris Zhong Message-ID: Date: Thu, 30 Nov 2017 10:27:49 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.4.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Doug Thank you for mentioning this patch. I think the focus of the discussion is: can we put the grf control bit to dts. The RK3399 has 2 Type-C phy, but only one DP controller, this "uphy_dp_sel" can help to switch these 2 phy. So I think this bit can be considered as a part of Type-C phy, these 2 phy have different bits, just similar to other bits (such as "pipe-status"). Put them to DTS file might be a accepted practice. On 2017年11月29日 07:32, Doug Anderson wrote: > Hi, > > On Thu, Feb 9, 2017 at 11:44 PM, Chris Zhong wrote: >> There are 2 Type-c PHYs in RK3399, but only one DP controller. Hence >> only one PHY can connect to DP controller at one time, the other should >> be disconnected. The GRF_SOC_CON26 register has a switch bit to do it, >> set this bit means enable PHY 1, clear this bit means enable PHY 0. >> >> If the board has 2 Type-C ports, the DP driver get the phy id from >> devm_of_phy_get_by_index, and then control this switch according to >> this id. But some others board only has one Type-C port, it may be PHY 0 >> or PHY 1. The dts node id can not tell us the correct PHY id. Hence move >> this switch to PHY driver, the PHY driver can distinguish between PHY 0 >> and PHY 1, and then write the correct register bit. >> >> >> >> Chris Zhong (4): >> Documentation: bindings: add uphy-dp-sel for Rockchip USB Type-C PHY >> arm64: dts: rockchip: add rockchip,uphy-dp-sel for Type-C phy >> phy: rockchip-typec: support DP phy switch >> drm/rockchip: cdn-dp: remove the DP phy switch >> >> Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt | 5 +++++ >> arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 ++ >> drivers/gpu/drm/rockchip/cdn-dp-core.c | 7 ------- >> drivers/phy/phy-rockchip-typec.c | 9 +++++++++ >> 4 files changed, 16 insertions(+), 7 deletions(-) > What ever happened to this series? It seemed like it just dropped on > the floor... > > There was a bit of contention on patch #3 > about the fact that we > were specifying addresses in the device tree vs. hardcoding them in > the driver. Any way we can just make a decision and go with it? > > > -Doug > > > -- Chris Zhong