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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-31cc3e45083sm7115312a91.2.2025.07.21.22.13.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 21 Jul 2025 22:13:42 -0700 (PDT) Message-ID: Date: Tue, 22 Jul 2025 13:13:34 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 3/4] arm64: dts: qcom: sa8775p: remove aux clock from pcie phy To: Konrad Dybcio , Johan Hovold Cc: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, jingoohan1@gmail.com, mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, johan+linaro@kernel.org, vkoul@kernel.org, kishon@kernel.org, neil.armstrong@linaro.org, abel.vesa@linaro.org, kw@linux.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, qiang.yu@oss.qualcomm.com, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com References: <20250718081718.390790-1-ziyue.zhang@oss.qualcomm.com> <20250718081718.390790-4-ziyue.zhang@oss.qualcomm.com> <86e14d55-8e96-4a2d-a9e8-a52f0de9dffd@oss.qualcomm.com> Content-Language: en-US From: Ziyue Zhang In-Reply-To: <86e14d55-8e96-4a2d-a9e8-a52f0de9dffd@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzIyMDA0MCBTYWx0ZWRfX1HPs8qDO5Zd1 PYLiNrSS6W7OqeLw+zHeOmJpU01V2H0jHLIGnUtHFrMntkfa8OcsQmUa5EQ82yFDMZnv+dsOXlI jXbxiQ0kv/LZbdzl2/Yyu0P9OmvS8SHjnoW4HIvIfeWrXI/guehbpWU0i5+Jtzo8bbSnU6Kg7fF FxZlForodeXl2CF7d+z8iAh5tAw6E1ZvK4Rlq4BFrG/oAIvNoj3eStTXUKThfUXUWFbfU0vguBg 7Ht4I71BrJWaMyukttCEox+XWQZ1TU7vr+ZzoY/7G8l8nKH6nzjNjfOidIdfhvVXTIApuTMh1hc kyAjbF0uYggrKndxUTrMtCXnmP6uu7n0YI7AB3x+OiUUpukn3hBvCPxUAoAGRlCl2Ei8uvAYtNT 2v6oJyHyMCBUPSNuQrTZaYUL+f+ubbMnEdAjIVn3IvWRnJeUNAahkL8b4C8Gm2kSyq88hOBc X-Authority-Analysis: v=2.4 cv=Jb68rVKV c=1 sm=1 tr=0 ts=687f1e08 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=MOqbobo4jd3P9B9bkYgA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-GUID: 2dy4o5EuVoiEHzt6r02xv63iQ2M56pfy X-Proofpoint-ORIG-GUID: 2dy4o5EuVoiEHzt6r02xv63iQ2M56pfy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-22_01,2025-07-21_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 adultscore=0 priorityscore=1501 clxscore=1015 phishscore=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 malwarescore=0 mlxscore=0 spamscore=0 impostorscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507220040 On 7/18/2025 6:53 PM, Konrad Dybcio wrote: > On 7/18/25 12:02 PM, Johan Hovold wrote: >> On Fri, Jul 18, 2025 at 04:17:17PM +0800, Ziyue Zhang wrote: >>> gcc_aux_clk is used in PCIe RC and it is not required in pcie phy, in >>> pcie phy it should be gcc_phy_aux_clk, so remove gcc_aux_clk and >>> replace it with gcc_phy_aux_clk. >> Expanding on why this is a correct change would be good since this does >> not yet seem to have been fully resolved: >> >> https://lore.kernel.org/lkml/98088092-1987-41cc-ab70-c9a5d3fdbb41@oss.qualcomm.com/ > I dug out some deep memories and recalled that _PHY_AUX_CLK was > necessary on x1e for the Gen4 PHY to initialize properly. This > can be easily reproduced: > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > index a9a7bb676c6f..d5ef6bef2b23 100644 > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > @@ -3312,7 +3312,7 @@ pcie3_phy: phy@1be0000 { > compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy"; > reg = <0 0x01be0000 0 0x10000>; > > - clocks = <&gcc GCC_PCIE_3_PHY_AUX_CLK>, > + clocks = <&gcc GCC_PCIE_3_AUX_CLK>, > <&gcc GCC_PCIE_3_CFG_AHB_CLK>, > <&tcsr TCSR_PCIE_8L_CLKREF_EN>, > <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>, > > ==> > [ 6.967231] qcom-qmp-pcie-phy 1be0000.phy: phy initialization timed-out > [ 6.974462] phy phy-1be0000.phy.0: phy poweron failed --> -110 > > And the (non-PHY_)AUX_CLK is necessary for at least one of them, as > removing it causes a crash on boot > > Konrad Hi Konrad, Johan I tried remove PHY_AUX_CLK in sa8775p platform like this, and it will cause a crash on boot. And I checked the clock documentation for sa8775p and found that the PHY_AUX_CLK  is also required. The changes are as follows: --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -7887,7 +7887,7 @@ pcie1_phy: phy@1c14000 {                 compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";                 reg = <0x0 0x1c14000 0x0 0x4000>; -               clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, +               clocks = <&gcc GCC_PCIE_1_AUX_CLK>,                          <&gcc GCC_PCIE_1_CFG_AHB_CLK>,                          <&gcc GCC_PCIE_CLKREF_EN>,                          <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, BRs Ziyue