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Fri, 17 Jul 2026 02:19:40 -0700 (PDT) X-Received: by 2002:a05:6a00:887:b0:847:e2c7:59c5 with SMTP id d2e1a72fcca58-84c294fc35bmr1785532b3a.49.1784279980040; Fri, 17 Jul 2026 02:19:40 -0700 (PDT) Received: from [10.219.57.117] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84c2adcd3dcsm676117b3a.24.2026.07.17.02.19.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 17 Jul 2026 02:19:39 -0700 (PDT) Message-ID: Date: Fri, 17 Jul 2026 14:49:32 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 11/11] arm64: dts: qcom: shikra: Add gpio-reserved-ranges to tlmm To: Konrad Dybcio , Vinod Koul , Frank Li , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Georgi Djakov , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Anurag Pateriya References: <20260702-shikra-dt-m1-v5-0-f911ac92720c@oss.qualcomm.com> <20260702-shikra-dt-m1-v5-11-f911ac92720c@oss.qualcomm.com> <9c1aab59-14b2-4811-b778-8e96645bd65b@oss.qualcomm.com> <97b205e8-5ab7-4205-b1dc-cbcb0497987d@oss.qualcomm.com> <986da1da-db2e-4d4a-b9d0-70482adaf4bd@oss.qualcomm.com> <4f641f13-a278-4465-8033-670c7279a7e3@oss.qualcomm.com> <1153ebbd-659f-4ba9-9317-66ece33423e9@oss.qualcomm.com> Content-Language: en-US From: Komal Bajaj In-Reply-To: <1153ebbd-659f-4ba9-9317-66ece33423e9@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=IMIyzAvG c=1 sm=1 tr=0 ts=6a59f3ad cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=lo2R6pnlw34kmT72REkA:9 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzE3MDA5MSBTYWx0ZWRfXwQSFIYE0uodW xfjN4yiqmaHBa8T2EixOFoK0j+KuGoP0oMSOGcuoC3dTT8JVKgm7yjek5/gondC1hSQ2r4KFc3T Tt9vuGUId71fR8/X8kCURscblMW+JuQwrPvZNPqh6AoyTnEFpo75VZ07t3XRfxAelB/VWrb3sW2 cA7MoeqgdYwNkOnSKAYUuEoAJ4etta238Ed8l+wXCjCTvotYpbujYc3sIECMbtNT88ptohvYWIH LQ+/0W7JvI11BLIZfktQNFZeOEGL0b7TUvLrl2qxe6cK8J6D39dDm9/ot3NcU/nIeZlNx6ZD1RK 5i3JErJ2TDwAp+Bu4chdmEkPL9S+yqVNa8qRWWeFNYJKEgBDLNRnq1tAZ7zcuyPdTfnmbK8NXGG E3Bm43Osn4h9ldCI2rfAc4MopwmogpPbRkK/GlpDRbg0SusjH6bCnW0iC4qouXi6K8D7YNNRSOx oXFxOjGODT2NPwTC5tQ== X-Proofpoint-GUID: l_NQuYKhjwViiYc-twxZSPieQi5PSKQy X-Proofpoint-ORIG-GUID: l_NQuYKhjwViiYc-twxZSPieQi5PSKQy X-Proofpoint-Spam-Info: AW1haW4tMjYwNzE3MDA5MSBTYWx0ZWRfX3O2+YLkR2szM hxXvmgMNSazWn3TVeYHsqvyun+y6HR0DXsJsNkPoTYoNTT/a3EVVWu1YN4Idsr3yzEA5qP0wz3Q 2CzjePZqjUMhR9uNJ/Wnd7Z0+sp2jdw= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-17_02,2026-07-15_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 suspectscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 adultscore=0 phishscore=0 malwarescore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607170091 On 7/17/2026 12:03 AM, Konrad Dybcio wrote: > On 7/15/26 3:41 PM, Komal Bajaj wrote: >> >> >> On 7/15/2026 3:57 PM, Konrad Dybcio wrote: >>> On 7/7/26 6:36 PM, Komal Bajaj wrote: >>>> On 7/2/2026 4:25 PM, Konrad Dybcio wrote: >>>>> On 7/2/26 11:50 AM, Komal Bajaj wrote: >>>>>> Add gpio-reserved-ranges property to the tlmm node for all three >>>>>> Shikra EVK variants (CQM, CQS, IQS) to mark GPIOs used by the >>>>>> SoC internally and not available for general use. >>>>> These are generally added to prevent non-secure access upon TLMM >>>>> probe, i.e. the board won't boot if some of them are not protected. >>>>> >>>>> I assume the proposed set contains both ones that are _absolutely >>>>> forbidden_ for Linux to touch, but also ones that are dedicated to >>>>> some specific purpose that Linux _shouldn't_ touch. >>>> Yes, some GPIOs are reserved for secure-world use and are therefore not accessible from the non-secure world. >>>> I will update the commit message accordingly. >>> I'm not sure how to read your response. In other words - is this >>> patch boot-critical? >> Yes, with Access Policy enabled, it becomes boot-critical. > Well then, I'm no less than surprised since we have DTs for 3 boards > in -next right now that I'm learning can't possibly boot.. > > I understand you might have disabled that at some point during the > development, but it's clearly not the configuration that's supported > by any means. Please make sure to take that into account next time. Development initially started with firmware builds that did not have Access Policy enabled. Recently, firmware has since been updated to enable Access Policy, which makes these GPIOs boot-critical and requires this change. If its needed, I can add Fixes tag. > > For this issue, since the pins seem common, perhaps moving them to > the SoM DTSI makes more sense. And this most definitely needs 'fixes' > tags. Makes sense. I'll move it to the SoM DTSI in the next revision. Thanks Komal > > Konrad