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X-CSE-ConnectionGUID: Ha9wYqHjT0qeHyN+2RgOnQ== X-CSE-MsgGUID: HnLOC+oaQUGZ5rH6GpZVZQ== X-IronPort-AV: E=McAfee;i="6800,10657,11732"; a="74829023" X-IronPort-AV: E=Sophos;i="6.23,126,1770624000"; d="scan'208";a="74829023" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Mar 2026 08:21:38 -0700 X-CSE-ConnectionGUID: obWNhz3JRdujbnFQyjP1wQ== X-CSE-MsgGUID: vGr1VKMdSrKMYUzbTkeBpw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,126,1770624000"; d="scan'208";a="222521878" Received: from rchatre-mobl4.amr.corp.intel.com (HELO [10.125.108.160]) ([10.125.108.160]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Mar 2026 08:21:36 -0700 Message-ID: Date: Tue, 17 Mar 2026 08:21:34 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] x86/cpu/centaur: Disable X86_FEATURE_FSGSBASE on Zhaoxin C4600 To: Tony W Wang-oc , me@ziyao.cc Cc: andrew.cooper3@citrix.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, linux-kernel@vger.kernel.org, mingo@redhat.com, stable@vger.kernel.org, tglx@kernel.org, x86@kernel.org, lukelin@viacpu.com, "TimGuo@zhaoxin.com" , cooperyan@zhaoxin.com, benjaminpan@viatech.com, QiyuanWang@zhaoxin.com, HerryYang@zhaoxin.com, "CobeChen@zhaoxin.com" References: <20260228173704.62460-1-me@ziyao.cc> <70139192-54e5-4a4b-bc96-1fe3ec4f7a0b@zhaoxin.com> <7d312ba6-58a0-48cb-92fa-d8094ddef21f@intel.com> <03a03ec8-4309-42ac-a13d-2fcc8396d547@intel.com> <08c3f1d4-326b-4a04-968c-23dd8ed14d0f@zhaoxin.com> From: Dave Hansen Content-Language: en-US Autocrypt: addr=dave.hansen@intel.com; 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charset=UTF-8 Content-Transfer-Encoding: 8bit > --- /dev/null > +++ b/arch/x86/include/asm/zhaoxin.h > @@ -0,0 +1,48 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +#ifndef _ASM_X86_ZHAOXIN_H > +#define _ASM_X86_ZHAOXIN_H > + > +#include > +#include > + > +#define    ZHAOXIN_MODEL_ZXC    VFM_MAKE(X86_VENDOR_ZHAOXIN, 6, 25) > +#define    CENTAUR_MODEL_ZXC    VFM_MAKE(X86_VENDOR_CENTAUR, 6, 15) > + > +struct x86_cpu_id naughty_list[] = { > +    X86_MATCH_VFM_STEPS(ZHAOXIN_MODEL_ZXC, 0, 3, 0), > +    X86_MATCH_VFM_STEPS(CENTAUR_MODEL_ZXC, 14, 15, 0), > +    {} > +}; Hi Tony, This is headed in the right direction, in a way. However, I think you might have missed a few things. Did you notice that this structure is in a .h file? We generally don't define data structures and variables in header files. You might want to take a quick look around the tree. Then, go try and #include this header in two different places. See what happens. > +void check_fsgsbase_bugs(void); > + > +void check_fsgsbase_bugs(void) > +{ Generally, compiler warnings are good things. They tell you that you've done something wrong. Simply throwing code in to silence them isn't a great practice. Remember the compiler warning you got without the function declaration? That was there to tell you that something is wrong. You placed definitions in a header, not declarations. But, adding a declaration before the definition made the compiler quiet. > +    u32 chip_pf, dummy, fixed_ucode; This is whitespace damaged, btw. I also prefer one variable per line u32 fixed_ucode; u32 chip_pf; u32 dummy; > +    if (!cpu_feature_enabled(X86_FEATURE_FSGSBASE)) > +        return; > + > +    if (!x86_match_cpu(naughty_list)) > +        return; Heh, also I was joking about 'naughty_list'. It would be best to give it a good symbolic, meaningful name. > +    native_rdmsr(MSR_ZHAOXIN_MFGID, dummy, chip_pf); This at least need commenting. What prevents this code from getting called on other vendors' CPUs? What about models of Zhaoxin CPUs that don't have this MSR? > +    /* chip_pf represents product version flag */ > +    chip_pf = (chip_pf >> 15) & 0x7; Please use the GENMASK macros here. > +    if (chip_pf == 0) > +        fixed_ucode = 0x20e; > +    if (chip_pf == 1) > +        fixed_ucode = 0x208; > + > +    if (intel_get_microcode_revision() >= fixed_ucode) > +        return; It's probably worth commenting why this is calling an "intel"_ function. > +    pr_warn_once("Broken FSGSBASE support, clearing feature\n"); > +    setup_clear_cpu_cap(X86_FEATURE_FSGSBASE); > +} > + > +#endif